Third-Order CDR Circuit for Residual Jitter Cancellation
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Solution Overview
Problem
Conventional clock and data recovery (CDR) circuits in digital communication systems, especially those using spread-spectrum clock signals, fail to completely cancel residual jitter, leading to performance and stability issues due to the limitations of first and second order digital loop filters.
Innovation Solution
A novel CDR circuit employing a third order finite state machine (FSM) with three accumulators connected in series, which generates a third order phase code to completely cancel residual jitter, improving jitter tolerance and system stability by rotating the clock signal based on this phase code.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a first order or second order digital loop filter is used in the CDR circuit, then the device complexity is reduced, but the residual jitter cannot be completely canceled leading to poor performance and stability
Solution Approach 1:
The patent changes the order parameter of the digital loop filter from conventional first or second order to third order. This parameter change enables the filter to completely cancel residual jitter while maintaining system stability with a phase margin of at least 60 degrees, resolving the contradiction between reliability and complexity by showing that a moderate increase in filter order achieves superior jitter cancellation without excessive complexity
Solution Approach 2:
The patent implements a feedback mechanism where the third order digital loop filter continuously monitors phase error between the recovered clock and incoming data, then adjusts the clock phase through a phase interpolator. This feedback loop enables complete cancellation of residual jitter by dynamically correcting phase deviations, thereby improving system reliability and stability
2Reliability
If a third order digital loop filter is used to completely cancel residual jitter, then the system stability and jitter tolerance are improved, but the device complexity increases
Solution Approach 1:
The patent increases the filter order parameter from second order to third order, which provides the additional degree of freedom needed to completely cancel residual jitter. The third order filter achieves superior jitter tolerance by eliminating the limitations of lower order filters, demonstrating that the moderate increase in complexity is justified by the significant improvement in reliability and jitter cancellation performance
Data Source
AI summary
Circuits and methods for performing a clock and data recovery are disclosed. In one example, a circuit is disclosed. The circuit includes an FSM. The FSM includes: a first accumulator, a second accumulator, and a third accumulator. The first accumulator is configured to receive an input phase code representing a phase timing difference between a data signal and a clock signal at each FSM cycle, to accumulate input phase codes for different FSM cycles, and to generate a first order phase code at each FSM cycle. The second accumulator is coupled to the first accumulator and configured to accumulate the input phase codes and first order phase codes for different FSM cycles, and to generate a second order phase code at each FSM cycle. The third accumulator is coupled to the second accumulator and configured to accumulate the input phase codes and second order phase codes for different FSM cycles, and to generate a third order phase code at each FSM cycle.