Unified Thread Address Mapping for Parallel Processors
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Solution Overview
Problem
Existing parallel thread processors require multiple distinct memory access instructions for different memory spaces, leading to inefficiency in programming due to the need for separate instruction sequences based on memory type.
Innovation Solution
A method for thread address mapping that computes a virtual address from a thread address within a unified address space, allowing a single load or store instruction to access multiple memory spaces, including thread-local, shared, and global memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple distinct memory access instructions are used for different memory spaces (thread-local, shared, global), then memory access precision and control are improved, but device complexity and programming complexity increase
Solution Approach 1:
The patent merges multiple distinct memory access instructions for different memory spaces into a single unified load/store instruction. The instruction uses a unified address space where thread-local, shared, and global memory are mapped to different address ranges. The memory system automatically routes accesses to the appropriate memory space based on the address range, eliminating the need for separate instructions while maintaining precise memory access control.
Solution Approach 2:
The unified load/store instruction is designed to be universal and can access all types of memory spaces (thread-local, shared, global) through address mapping. The instruction set is simplified to use a single type of pointer address that can reference any memory space, making the instruction multi-functional while maintaining the ability to precisely control access to different memory regions through address encoding.
2Measurement precision
If separate instruction sequences are required for each memory type, then memory access control is improved, but ease of operation and programming efficiency deteriorate
Solution Approach 1:
The patent combines multiple separate instruction sequences into a single unified load/store instruction that can access all memory spaces. Programmers use one instruction type with different address values to access thread-local, shared, or global memory, eliminating the need to learn and maintain separate instruction sequences while preserving precise control over memory access behavior through address range encoding.
3Reliability
If multiple distinct memory access instructions are used, then reliability of memory access is improved, but productivity and processing efficiency worsen
Solution Approach 1:
The patent merges multiple memory access instructions into a single unified instruction that maintains reliable access to all memory spaces through address mapping. The memory system automatically routes accesses to the appropriate memory space based on address ranges, ensuring reliable memory access while improving processing efficiency by reducing instruction decode complexity and enabling more efficient pipeline execution.
Data Source
AI summary
A method for thread address mapping in a parallel thread processor. The method includes receiving a thread address associated with a first thread in a thread group; computing an effective address based on a location of the thread address within a local window of a thread address space; computing a thread group address in an address space associated with the thread group based on the effective address and a thread identifier associated with a first thread; and computing a virtual address associated with the first thread based on the thread group address and a thread group identifier, where the virtual address is used to access a location in a memory associated with the thread address to load or store data.