Thread Atomicity for Unambiguous Parameter Sampling
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Solution Overview
Problem
In heterogeneous multi-core or multi-threaded processor environments, existing redundancy schemes face challenges in obtaining accurate and synchronized counter and state samples due to bus latencies and separate read cycles, leading to ambiguous results and loss of information.
Innovation Solution
The implementation of thread atomicity with deterministic synchronization, where thread requests are masked and commands are executed only after bus activity ceases and routines are completed, ensuring synchronous and lossless operations for counter and state sampling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple transmitters each have their own thread running on separate processor cores to control transmission and protocol state machine, then transmission control and protocol execution are improved, but accurate simultaneous sampling of counters and states becomes impossible due to bus latencies and separate read cycles
Solution Approach 1:
The system separates the sampling control mechanism into individual thread masks for each transmitter thread. Each thread has its own mask bit that can be independently controlled, allowing the CPU to selectively mask specific threads during sampling operations while leaving others unaffected. This segmentation enables precise control over which threads are paused during the sampling window.
Solution Approach 2:
A new intermediary mechanism is introduced: a mask register and associated control logic that sits between the CPU and the thread execution units. This intermediary allows the CPU to atomically mask/unmask threads without directly interfering with their execution, providing a clean interface for synchronization. The mask register acts as a mediator that coordinates thread pausing with the sampling operation.
2Ease of operation
If the CPU performs multiple temporally dislocated read operations to obtain counter and state values, then reading flexibility is maintained, but deterministic synchronization and coherent snapshots cannot be achieved
Solution Approach 1:
The system performs preliminary action by masking the thread requests before the actual sampling read operations occur. The CPU sets the mask bit in advance, which prevents the thread from making any bus transactions or modifying counters/states during the sampling window. This preliminary masking ensures that when the CPU subsequently performs its read operations, the values it reads are guaranteed to be coherent and from the same moment in time.
Solution Approach 2:
The masking mechanism maintains continuity by ensuring that the thread's useful action (data transmission and counter updating) is seamlessly paused during sampling and then resumed without interruption or data loss. The mask is temporarily applied only for the duration of the sampling operation, and the thread continues its normal operation immediately after unmasking, maintaining continuous productive work.
3Reliability
If cache-based approaches are used to provide deterministic synchronization in homogeneous core complexes, then cache coherency is improved, but hardware complexity increases and the approach cannot be applied to heterogeneous systems without data cache hardware
Solution Approach 1:
The invention extracts the synchronization function from the cache subsystem and relocates it to a simpler, dedicated masking mechanism. Instead of relying on complex cache coherency protocols and hardware to enforce synchronization, the system removes this dependency by using software-controlled thread masking that works independently of cache architecture. This extraction simplifies the hardware requirements while maintaining synchronization reliability.
Solution Approach 2:
The masking mechanism is designed as a universal solution that works across heterogeneous processor architectures. Unlike cache-based approaches that require specific homogeneous core complexes with data cache hardware, the thread masking mechanism can be implemented on any processor that supports register operations, including heterogeneous systems with different core types, embedded processors, and systems without traditional cache hierarchies.
4Reliability
If the counter or state is reset after the read operation, then counter overflow is prevented, but information may be lost during the period between read and write reset
Solution Approach 1:
The system applies preliminary anti-action by masking the thread before the counter is reset. The mask prevents the thread from executing any operations that could modify the counter or state during the critical window between the CPU's read operation and the subsequent reset write operation. This preliminary masking counteracts the potential harm of information loss by ensuring the thread remains inert during the entire read-reset interval.
Data Source
AI summary
Apparatuses, methods, and systems are configured to perform unambiguous parameter sampling in a heterogeneous multi-core or multi-threaded environment by masking one or more thread requests; and, in response to bus activity ceasing for the one or more masked thread requests and completing any routine being processed for the one or more masked threads, processing a command by executing at least one of a command routine or a command thread, wherein the command routine or the command thread reads the parameter using thread atomicity with deterministic synchronization. One or more thread requests may be selected for masking by monitoring thread activity for each of a plurality of threads.