Thread-Specific Clock Control for Processor Power Optimization
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Solution Overview
Problem
Conventional processors lack a flexible mechanism for controlling clock speed on a per-thread basis, leading to inefficient power management, wasted cycles, and potential functional failures due to shared state inheritance during interrupts and context switching.
Innovation Solution
A processor architecture with thread-specific clock control, utilizing a clock divider and status register with clock control bits to generate different clock frequencies for each thread, allowing explicit software control and automatic adjustment during interrupts, without requiring RTOS modifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a processor runs at high clock frequency, then processing speed is improved, but power consumption increases and wasted clock cycles occur when full speed is not required
Solution Approach 1:
The patent segments the clock control mechanism by introducing thread-specific clock control bits that allow different threads to have different clock frequency requirements. This enables the processor to divide its operation into threads that can independently specify their needed clock speeds, avoiding the waste of running all threads at maximum frequency when not needed.
Solution Approach 2:
The patent applies local quality by allowing different threads to have different clock frequencies based on their specific requirements. Each thread can be assigned a clock frequency appropriate to its computational needs, rather than applying a uniform high frequency to all threads, thus optimizing power consumption locally for each thread.
2Productivity
If a processor runs at full speed, then performance is improved, but flexibility in power management is reduced
Solution Approach 1:
The patent introduces dynamic power management flexibility by allowing the clock frequency to be dynamically adjusted on a per-thread basis. The system can adaptively change clock frequencies according to the specific requirements of each thread, providing both high performance when needed and power savings when not needed, thus achieving flexibility in power management.
3Use of energy by moving object
If clock frequency is controlled on a per-thread basis, then power optimization is improved, but device complexity increases
Solution Approach 1:
The patent extracts the clock control functionality into separate thread-specific clock control bits that are independent of the main thread context. This separation allows the clock control mechanism to be simplified while still achieving per-thread power optimization, as the control bits can be directly associated with each thread without requiring complex shared state management.
4Ease of operation
If shared state is inherited during context switching, then simplicity is maintained, but functional failures occur and interrupt handling efficiency is reduced
Solution Approach 1:
The patent implements copying by creating independent copies of clock control bits for each thread context. When threads are switched, each thread has its own dedicated clock control bits that are copied into the thread context, eliminating the problem of inherited shared state while maintaining simplicity through the straightforward copy operation.
5Measurement precision
If thread-specific clock control bits are stored in status register, then control precision is improved, but latency increases
Solution Approach 1:
The patent applies preliminary action by pre-associating clock control bits with each thread context before execution. The clock control bits are prepared and stored in the thread context in advance, so when a thread is scheduled, the appropriate clock frequency is already configured, minimizing the latency of clock frequency changes while maintaining precise control.
Data Source
AI summary
The present invention provides a processor comprising: an execution unit arranged to execute a plurality of program threads, clock generating means for generating first and second clock signals, and storage means for storing at least one thread-specific clock-control bit. The execution unit is configured to execute a first one of the threads in dependence on the first clock signal and to execute a second one of the threads in dependence on the second clock signal. The clock generating means is operable to generate the second clock signal with the second frequency selectively differing from the first frequency in dependence on the at least one clock-control bit. A corresponding method and computer program product are also provided.