Thread Coordination Opcodes for Precise Multi-Thread Synchronization

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Solution Overview

Problem

Existing multi-threading techniques fail to reliably synchronize independent threads in time, leading to suboptimal performance and quality issues in applications controlling independent components or devices, such as optical sensing devices.

Innovation Solution

Implementing thread coordination opcodes that suspend and resume thread execution based on matching identifiers and coordination counts, allowing synchronization and sequencing of multiple threads at an instant of time, with optional thread delay opcodes for precise timing control.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple threads are executed concurrently using existing multi-threading techniques, then tasks can run in parallel improving productivity, but the threads cannot be reliably synchronized in time leading to poor measurement precision

Engineering Contradiction:
Improveparallel execution of tasksVSAvoidsynchronization accuracy of threads
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The patent introduces thread coordination opcodes as intermediary synchronization points that mediate between independently executing threads. These opcodes act as mediators that allow threads to wait for specific coordination events (such as completion of certain operations or arrival of data) before proceeding, enabling precise temporal synchronization while maintaining parallel execution. The coordinator thread uses these opcodes to control the timing and sequencing of operations across multiple threads.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If thread synchronization is implemented using existing techniques, then some coordination between threads can be achieved, but the synchronization is not reliable enough for applications controlling independent components or devices

Engineering Contradiction:
Improvethread synchronization reliabilityVSAvoidcomplexity of synchronization mechanism
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements self-service synchronization where each thread independently encounters and processes thread coordination opcodes based on its own execution flow. Threads autonomously determine when to wait for coordination events and when to proceed, without requiring complex external synchronization control. The synchronization mechanism serves itself by using the natural execution order and coordination points within the thread code, reducing the need for external synchronization overhead.

Inventive Principle:
Principle #25Self-service

3Measurement precision

If threads are suspended and resumed frequently for coordination, then synchronization precision is improved, but execution efficiency and productivity may deteriorate

Engineering Contradiction:
Improvetiming accuracy of thread executionVSAvoidthread execution efficiency
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent applies preliminary action by having threads encounter thread coordination opcodes at predetermined synchronization points in their execution flow. These opcodes are placed strategically in the code at locations where coordination is needed, allowing threads to proactively wait for required events before proceeding with critical operations. This approach minimizes unnecessary suspensions by only pausing threads at essential coordination points rather than continuously checking synchronization conditions.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20250307034A1Enabling synchronization and sequencing of multiple threads
Publication Date: 2025.10.02 WELLS FARGO BANK NA
  • US20250307034A1 patent drawing
  • US20250307034A1 patent drawing
  • US20250307034A1 patent drawing

AI summary

In some implementations, a computing device may execute a first thread and may execute a second thread. The computing device may encounter, based on executing the first thread, a first thread coordination operation code (opcode) that is included in the first thread. The computing device may suspend, based on encountering the first thread coordination opcode, execution of the first thread. The computing device may encounter based on executing the second thread, and after suspending execution of the first thread, a second thread coordination opcode that is included in the second thread. The computing device may determine, based on encountering the first thread coordination opcode and encountering the second thread coordination opcode, that a thread coordination event has occurred. The computing device may resume, based on determining that the thread coordination event has occurred, execution of the first thread.