Thread Criticality-Based Memory Request Scheduling

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Solution Overview

Problem

Existing memory scheduling techniques in computing systems are inefficient as they do not account for interactions among multiple threads executing concurrently, leading to increased execution times and resource idleness due to critical sections, which can cause threads to block each other, thereby degrading system performance.

Innovation Solution

A memory request scheduling method that prioritizes memory requests based on thread criticality, which is determined by the number of critical sections executed and the number of threads blocked by a thread, using a criticality graph to maintain and update thread criticality values, and incorporating application priority to prevent starvation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If memory requests are scheduled using traditional prioritization methods, then memory access speed is maintained, but thread blocking and critical section delays increase execution time

Engineering Contradiction:
Improvememory access speedVSAvoidthread execution time
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The patent implements dynamic memory request scheduling by adjusting priority levels based on real-time thread criticality. The scheduler dynamically modifies memory request priorities according to the current execution state of threads, specifically whether threads are in critical sections or blocking each other, thereby optimizing memory access timing to reduce overall execution time while maintaining speed.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the scheduling parameter from static priority to dynamic priority based on thread criticality. By introducing criticality levels (e.g., normal, high, critical) that vary with execution state, the system adjusts memory request handling parameters in real-time to accommodate thread blocking scenarios, reducing execution time without sacrificing memory access performance.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If threads execute concurrently with critical sections, then system productivity increases, but resource idleness and thread blocking occur

Engineering Contradiction:
Improvesystem throughputVSAvoidresource idleness
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The patent implements a feedback mechanism where the scheduler continuously monitors thread execution states, particularly whether threads are in critical sections or blocking each other. This feedback information is used to adjust memory request priorities dynamically, allowing the system to respond to real-time conditions and reduce resource idleness by prioritizing memory access for blocked threads.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent applies preliminary action by proactively identifying threads that will be blocked in critical sections and preemptively adjusting their memory request priorities before blocking occurs. This allows the system to prepare for upcoming resource conflicts and reduce idleness by ensuring critical threads receive timely memory access.

Inventive Principle:
Principle #10Preliminary action

3Device complexity

If memory requests are prioritized without considering thread interactions, then scheduling simplicity is maintained, but starvation of lower-priority threads occurs

Engineering Contradiction:
Improvescheduling complexityVSAvoidthread execution reliability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent applies local quality by differentiating memory request scheduling based on the specific characteristics of each thread and its current execution state. Instead of uniform scheduling, the system assigns different priority levels to memory requests depending on whether the originating thread is in a critical section, blocking others, or ready to execute, thereby ensuring reliable thread execution while managing complexity locally.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS8850131B2Memory request scheduling based on thread criticality
Publication Date: 2014.09.30 ADVANCED MICRO DEVICES INC
  • US8850131B2 patent drawing
  • US8850131B2 patent drawing
  • US8850131B2 patent drawing

AI summary

A method includes scheduling a memory request requested by a thread executing on a processing system. The scheduling is based on at least one of a number of critical sections being executed on the processing system by the thread and a number of other threads executing on the processing system being blocked from execution on the processing system by execution of the thread. In at least one embodiment of the invention, the thread is associated with a first application of a plurality of applications executing on the processing system and the scheduling is further based on an indicator of application priority.