Dynamic Thread Decomposition for Compute-Near-Memory Scheduling

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Solution Overview

Problem

Existing computer architectures face performance constraints due to significant time and energy consumption in data movement between processors and memory, limiting compute efficiency and capacity.

Innovation Solution

Implementing a compute-near-memory (CNM) system with hybrid threading processors and custom compute fabrics, utilizing a divide and conquer strategy for thread scheduling and dynamic thread creation to enhance parallel processing efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If data is moved between processors and memory in conventional architectures, then data access is enabled, but significant time and energy are consumed

Engineering Contradiction:
Improvedata access speedVSAvoidtime consumption for data movement
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The system segments the monolithic processor into multiple processing elements (PEs) that can operate independently. Each PE has its own execution units and can access memory or cache locally, reducing the need for data movement across the entire system and thereby decreasing time consumption for data access.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a three-dimensional stacked architecture with multiple layers. Processing elements are distributed across different vertical layers, with each layer having access to local memory or cache. This spatial reorganization reduces data movement distance and time by enabling local access within the same or adjacent layers.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Speed

If data is moved between processors and memory in conventional architectures, then data access is enabled, but significant energy is consumed

Engineering Contradiction:
Improvedata access speedVSAvoidenergy consumption for data movement
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

By segmenting the system into multiple PEs with local memory or cache resources, the patent eliminates the need for frequent data movement across the entire memory bus. Each PE can access its local memory or cache without consuming energy for long-distance data transfer, significantly reducing overall energy consumption.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces on-chip caches and buffer memory as intermediary storage between the processing elements and main memory. Data can be cached locally in these intermediaries, allowing PEs to access frequently used data without energY-intensive transfers to and from main memory, thus reducing energy consumption while maintaining access speed.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If thread scheduling is optimized in CNM systems, then parallel processing efficiency is improved, but system complexity increases

Engineering Contradiction:
Improveparallel processing efficiencyVSAvoidthread scheduling system complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The thread scheduling system is designed to be dynamic and adaptive rather than static. The scheduler can dynamically allocate threads to processing elements based on current system state, workload characteristics, and resource availability. This dynamic approach improves parallel processing efficiency while managing complexity through event-driven scheduling decisions rather than complex pre-configured schedules.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements self-scheduling capabilities where processing elements can autonomously select and execute available threads from a thread pool without requiring complex centralized scheduling decisions. Each PE monitors its own workload and independently picks threads to execute, simplifying the overall scheduling system while maintaining high parallel processing efficiency through distributed decision-making.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS20250355705A1Dynamic decomposition and thread allocation
Publication Date: 2025.11.20 MICRON TECHNOLOGY INC
  • US20250355705A1 patent drawing
  • US20250355705A1 patent drawing
  • US20250355705A1 patent drawing

AI summary

Devices and techniques for thread scheduling control and memory splitting in a processor are described herein. An apparatus includes a hardware interface configured to receive a first request to execute a first thread, the first request including an indication of a workload; and processing circuitry configured to: determine the workload to produce a metric based at least in part on the indication; compare the metric with a threshold to determine that the metric is beyond the threshold; divide, based at least in part on the comparison, the workload into a set of sub-workloads consisting of predefined number of equal parts from the workload; create a second request to execute a second thread, the second request including a first member of the set of sub-workloads; and process a second member of the set of sub-workloads in the first thread.