Thread Group Divergence Optimization in Graphics Processors
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Solution Overview
Problem
Existing graphics processing systems face inefficiencies in processing divergent threads due to branch instructions and predicated instructions, leading to reduced throughput and increased latency.
Innovation Solution
The technology optimizes divergent processing by grouping execution threads into thread groups and using an execution thread issuing circuit to determine whether active threads from different thread groups use different execution lanes, allowing simultaneous execution across multiple lanes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If threads are processed sequentially in lockstep within a thread group, then instruction fetch and scheduling resources can be shared, but execution lanes are underutilized when divergent processing occurs
Solution Approach 1:
The patent segments thread groups into multiple sub-groups based on divergence characteristics. Each sub-group is processed independently on separate execution lanes, allowing parallel execution of divergent threads while maintaining resource sharing within each sub-group. This segmentation resolves the contradiction by enabling both resource efficiency and lane utilization.
Solution Approach 2:
The patent introduces a new dimension of processing by allowing different thread groups to be processed simultaneously on different execution lanes rather than strictly sequentially. This dimensional change in the processing architecture enables parallel execution of divergent threads across multiple lanes while maintaining the lockstep execution model within each lane.
2Loss of energy
If divergent threads are processed by restricting active lanes to only those needed by the subset of threads, then resource consumption is reduced, but throughput decreases
Solution Approach 1:
The patent segments the thread group into multiple sub-groups based on their divergence patterns. Each sub-group is assigned to a separate execution lane, allowing all lanes to remain active simultaneously processing different sub-groups. This eliminates the need to restrict lane activity while maintaining efficient resource usage within each lane.
Solution Approach 2:
The patent merges multiple sub-group processing operations across different execution lanes into a unified processing framework. By coordinating the execution of multiple sub-groups across multiple lanes, the system achieves high throughput while maintaining efficient resource consumption through the segmented approach.
3Productivity
If multiple thread groups with divergent processing are executed simultaneously, then throughput increases, but resource contention increases
Solution Approach 1:
The patent segments thread groups into sub-groups that are processed on dedicated execution lanes, reducing resource contention by isolating resource usage within each lane. This segmentation allows multiple thread groups to execute simultaneously with minimal interference between them.
Solution Approach 2:
The patent performs preliminary analysis of thread group divergence characteristics before execution, organizing threads into sub-groups that will be processed on specific lanes. This preliminary organization prevents resource contention during execution by pre-assigning resources based on predicted usage patterns.
Data Source
AI summary
A data processor is disclosed in which groups of execution threads comprising a thread group can execute a set of instructions in lockstep, and in which a plurality of execution lanes can perform processing operations for the execution threads. In response to an execution thread issuing circuit determining whether a portion of active threads of a first thread group and a portion of active threads of a second thread group use different execution lanes of the plurality of execution lanes, the execution thread issuing circuit issuing both the portion of active threads of a first thread group and a portion of active threads of a second thread group for execution. This can have the effect of increasing data processor efficiency, thereby increasing throughput and reducing latency.