Thread Hog Mitigation in Threaded Processor Resource Arbitration

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Solution Overview

Problem

In computing systems with dynamic resource allocation, thread hogs can occur when a thread accumulates a disproportionate share of shared resources and is slow to deallocate, leading to throughput losses for both the hog thread and other threads sharing the resources, especially during long latency operations like last-level data cache misses.

Innovation Solution

The control logic detects load misses with latency greater than a threshold, identifying potential thread hogs, and initiates a pipeline flush by selecting the load instruction or younger instructions for replay, holding younger instructions at a pipeline stage until the load completes, to mitigate resource imbalances and prevent starvation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If dynamic resource allocation is used among multiple threads, then overall throughput performance is improved, but thread hogs can accumulate disproportionate share of shared resources and become slow to deallocate, causing throughput losses

Engineering Contradiction:
Improveoverall throughput performanceVSAvoidthread hog behavior
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The control logic continuously monitors resource allocation status and thread execution behavior, detecting when a thread has accumulated a disproportionate share of shared resources. This feedback mechanism enables the system to identify thread hogs and trigger appropriate mitigation actions, resolving the contradiction by maintaining dynamic allocation benefits while preventing harmful resource monopolization

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system dynamically adjusts resource allocation policies based on real-time thread behavior. When a thread hog is detected, the control logic can dynamically flush the pipeline for that thread, forcing deallocation of accumulated resources. This dynamic response allows the system to maintain high throughput for legitimate threads while preventing thread hogs from causing throughput losses

Inventive Principle:
Principle #15Dynamics

2Reliability

If a thread accumulates disproportionate share of shared resources during long latency operations, then the thread may continue execution, but other threads sharing the same resource experience throughput losses

Engineering Contradiction:
Improvethread execution continuityVSAvoidthroughput for other threads
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The control logic acts as an intermediary between threads and shared resources, mediating resource allocation and deallocation. When a thread hog is detected during long latency operations, the control logic intervenes by flushing the pipeline for that thread, forcing it to release accumulated resources. This mediation ensures that thread execution continuity is maintained through controlled interruption while preventing throughput losses for other threads by redistributing resources

Inventive Principle:
Principle #24Intermediary (Mediator)

3Ease of operation

If pipeline flush is initiated for thread hog mitigation, then resource allocation fairness is improved, but instructions must be replayed causing time loss

Engineering Contradiction:
Improveresource allocation fairnessVSAvoidinstruction replay time
Core Design Contradiction:
Ease of operationVSLoss of time

Solution Approach 1:

The control logic extracts and identifies the specific load instruction that caused the thread hog condition, then initiates pipeline flush from that point. By precisely extracting the problematic instruction rather than flushing the entire pipeline, the system achieves resource allocation fairness while minimizing instruction replay time. This targeted approach reduces the time loss compared to blanket pipeline flushes

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS9665375B2Mitigation of thread hogs on a threaded processor and prevention of allocation of resources to one or more instructions following a load miss
Publication Date: 2017.05.30 ORACLE INT CORP
  • US9665375B2 patent drawing
  • US9665375B2 patent drawing
  • US9665375B2 patent drawing

AI summary

Systems and methods for efficient thread arbitration in a threaded processor with dynamic resource allocation. A processor includes a resource shared by multiple threads. The resource includes an array with multiple entries, each of which may be allocated for use by any thread. Control logic detects a load miss to memory, wherein the miss is associated with a latency greater than a given threshold. The load instruction or an immediately younger instruction is selected for replay for an associated thread. A pipeline flush and replay for the associated thread begins with the selected instruction. Instructions younger than the load instruction are held at a given pipeline stage until the load instruction completes. During replay, this hold prevents resources from being allocated to the associated thread while the load instruction is being serviced.