Thread Mapping Heterogeneous Cores Execution Characteristics

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Solution Overview

Problem

In multi-core computer systems with heterogeneous hardware, existing methods fail to efficiently map threads to appropriate processor cores based on execution characteristics, leading to suboptimal performance due to differences in hardware capabilities among cores.

Innovation Solution

A thread mapping system that utilizes performance counters and execution profiles to dynamically assign threads to cores with matching capabilities, considering factors like cache usage and instruction sets, and allows for reassignment during thread execution to optimize performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If threads are mapped to heterogeneous cores without considering execution characteristics, then device complexity is reduced, but system performance deteriorates

Engineering Contradiction:
Improvesystem performanceVSAvoidthread mapping complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The system changes the parameter of thread mapping from static to dynamic by monitoring execution characteristics (cache miss rates, branch prediction accuracy, floating-point operation counts) and reassigning threads to different cores based on these changing parameters. This allows the system to adapt to varying workloads and maximize performance utilization of heterogeneous core capabilities.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The system implements feedback mechanisms by continuously monitoring thread execution characteristics on each core and using this information to make informed decisions about thread reassignment. Performance counters track metrics such as cache efficiency and instruction execution rates, providing feedback that drives the thread migration decisions to optimize overall system performance.

Inventive Principle:
Principle #23Feedback

2Productivity

If threads are dynamically reassigned based on execution characteristics, then productivity is improved, but device complexity increases

Engineering Contradiction:
Improvethread execution efficiencyVSAvoidmapping system complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The system enables threads to effectively self-optimize by monitoring their own execution characteristics and triggering reassignment when performance thresholds are exceeded. Each thread's performance is independently evaluated, and the thread can be migrated to a more suitable core without requiring complex centralized control, thereby reducing overall system complexity while maintaining high productivity.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The thread mapping system is segmented into independent monitoring and decision-making units for each core, where execution characteristics are tracked separately and reassignment decisions are made based on localized performance data. This modular approach reduces the complexity of global optimization while still achieving system-wide performance improvements through coordinated thread migration.

Inventive Principle:
Principle #1Segmentation

3Productivity

If thread reassignment is performed frequently, then productivity is improved, but loss of time increases

Engineering Contradiction:
Improveprocessing efficiencyVSAvoidthread migration time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The system implements dynamic threshold-based reassignment where the frequency and timing of thread migrations are adjusted based on the rate of change in execution characteristics. When performance degradation exceeds a dynamic threshold, reassignment is triggered; otherwise, threads remain on their current core. This dynamic approach balances the need for optimization with the cost of migration, preventing excessive reassignments while maintaining high productivity.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS9569270B2Mapping thread phases onto heterogeneous cores based on execution characteristics and cache line eviction counts
Publication Date: 2017.02.14 MERCURY KINGDOM ASSETS LIMITED
  • US9569270B2 patent drawing
  • US9569270B2 patent drawing
  • US9569270B2 patent drawing

AI summary

Techniques are generally described for mapping a thread onto heterogeneous processor cores. Example techniques may include associating the thread with one or more predefined execution characteristics, assigning the thread to one or more heterogeneous processor cores based on the one or more predefined execution characteristics, and/or executing the thread by the respective assigned heterogeneous processor cores.