Thread Migration for Power Efficiency in Parallel Processing

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Solution Overview

Problem

In multi-core parallel computing systems, power inefficiencies arise due to imbalances in thread execution speeds, leading to idle processing cores and wasted energy, as faster cores wait for slower ones to complete tasks, especially in tera-scale environments with numerous cores.

Innovation Solution

The selective migration of threads among processing cores, combined with meeting-point synchronization mechanisms, allows for the redistribution of threads and adjustment of power states to reduce idle time and energy consumption by prioritizing critical threads and slowing down non-critical ones, thereby improving power efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If threads are executed in parallel on multiple cores without migration, then processing speed is improved, but power efficiency deteriorates due to idle cores waiting for slow threads

Engineering Contradiction:
Improveprocessing speedVSAvoidpower efficiency
Core Design Contradiction:
SpeedVSLoss of energy

Solution Approach 1:

The system dynamically migrates threads between processing cores based on real-time execution progress. Fast threads are identified and moved to different cores, allowing original cores to enter low-power states, while slow threads continue execution on their original cores. This dynamic adaptation resolves the contradiction by making the system flexible rather than static.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the execution parameters of threads by migrating them between cores. By altering which core executes which thread, the system optimizes power consumption without sacrificing overall processing speed. The migration decision is based on comparing execution speeds and predicting completion times.

Inventive Principle:
Principle #35Parameter changes

2Loss of energy

If cores are put to sleep to save power, then energy consumption is reduced, but system complexity increases due to wake-up management

Engineering Contradiction:
Improveenergy consumptionVSAvoidsystem complexity
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The system introduces a power management unit as an intermediary that coordinates thread migration and core power state transitions. This mediator manages the complexity of waking up cores and ensuring thread continuity, isolating the complexity from the main processing logic and making the system more manageable.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Loss of energy

If thread execution is reconfigured on a particular core, then some power efficiency improvement is achieved, but limited efficiency gains are obtained due to constraints of the specific core-thread pairing

Engineering Contradiction:
Improvepower efficiencyVSAvoidefficiency improvement potential
Core Design Contradiction:
Loss of energyVSProductivity

Solution Approach 1:

The system segments the thread execution process by separating fast threads from slow threads through migration. Fast threads are moved to dedicated cores that can enter low-power states, while slow threads remain on their original cores. This segmentation allows independent optimization of power consumption for different thread types without compromising overall productivity.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS8806491B2Thread migration to improve power efficiency in a parallel processing environment
Publication Date: 2014.08.12 INTEL CORP
  • US8806491B2 patent drawing
  • US8806491B2 patent drawing
  • US8806491B2 patent drawing

AI summary

A method and system to selectively move one or more of a plurality threads which are executing in parallel by a plurality of processing cores. In one embodiment, a thread may be moved from executing in one of the plurality of processing cores to executing in another of the plurality of processing cores, the moving based on a performance characteristic associated with the plurality of threads. In another embodiment of the invention, a power state of the plurality of processing cores may be changed to improve a power efficiency associated with the executing of the multiple threads.