Hardware Thread Queue Control for Precondition-Based Accelerator Dispatch

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Solution Overview

Problem

Software-based thread management in processor multithreading scenarios incurs significant computational overhead, particularly in low-cost hardware platforms, leading to inefficiencies in resource utilization, increased power consumption, and reduced system throughput.

Innovation Solution

A hardware-based thread allocation controller that manages processor threads through hardware programming, reducing computational overhead by directly allocating and scheduling threads to hardware accelerators without software intervention.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If software-based thread management is used in processor multithreading, then thread allocation flexibility is maintained, but computational overhead increases and system throughput decreases

Engineering Contradiction:
Improvesystem throughputVSAvoidcomputational overhead
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent replaces software-based thread management with a hardware-based thread allocation controller that uses hardware programming to allocate processor threads to hardware accelerators. This substitution of software control with hardware control eliminates the computational overhead associated with software thread management while maintaining thread allocation flexibility through configurable hardware logic.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Use of energy by stationary object

If hardware-based thread allocation is implemented, then computational overhead is reduced and power consumption decreases, but device complexity increases

Engineering Contradiction:
Improvepower consumptionVSAvoidhardware controller complexity
Core Design Contradiction:
Use of energy by stationary objectVSDevice complexity

Solution Approach 1:

The hardware thread allocation controller is designed to perform multiple functions including thread queue management, precondition verification, and dynamic thread-to-accelerator allocation. By consolidating these functions into a single multi-functional hardware component, the patent reduces overall system complexity compared to having separate hardware modules for each function while still achieving reduced power consumption through hardware-based control.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Productivity

If processor threads are queued and preconditions are checked before execution, then resource utilization improves, but execution delay increases

Engineering Contradiction:
Improveresource utilizationVSAvoidthread execution delay
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The hardware thread allocation controller performs preliminary actions by pre-queuing processor threads and verifying preconditions before execution is required. Threads are placed in a thread queue with their preconditions checked in advance, allowing the system to prepare execution contexts ahead of time. This preliminary preparation reduces actual execution delay while maintaining high resource utilization through efficient queue management.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP4650963A1Hardware thread allocation controller
Publication Date: 2025.11.19 MICROSOFT TECHNOLOGY LICENSING LLC
  • EP4650963A1 patent drawingFigure 1
  • EP4650963A1 patent drawingFigure 2
  • EP4650963A1 patent drawingFigure 3A

AI summary

A method (200) for a hardware thread allocation controller (110) of a computing device (100) includes receiving, at the hardware thread allocation controller (110), a processor thread (104) including one or more processing commands (106) to be executed, and one or more preconditions (108) for execution of the processor thread (104). The processor thread (104) is stored in a thread queue (308) of the hardware thread allocation controller (110). Based at least in part on detecting that the one or more preconditions (108) for execution are met, the processor thread (104) is assigned to a hardware accelerator (112) of the computing device (100) for execution, wherein the hardware thread allocation controller (110) is configured to receive the processor thread (104), store the processor thread (104) in the thread queue (308), and assign the processor thread (104) to the hardware accelerator (112) through hardware programming of the hardware thread allocation controller (110).