Thread Scheduler Partition Schedule Hardware Thread Control
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Solution Overview
Problem
Existing multi-thread processor techniques require the interposition of a partition manager to deactivate hardware threads, leading to processing overhead and impaired processor capacity.
Innovation Solution
A semiconductor device with multiple hardware threads, an execution unit, and a scheduler that generates a thread select signal based on partition and thread schedules, allowing for independent switching between occupied and unoccupied states without relying on a host system or partition manager.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a partition manager is used to control hardware thread activation and deactivation, then thread management and partition control are achieved, but processing overhead increases and processor capacity is impaired
Solution Approach 1:
The patent extracts the thread management functionality from the partition manager (host system) and embeds it directly into the scheduler of the multi-thread processor. The scheduler now independently controls hardware thread activation and deactivation based on partition schedules, eliminating the need for partition manager intervention and reducing processing overhead.
Solution Approach 2:
The multi-thread processor becomes self-sufficient in managing its own hardware threads. The scheduler autonomously determines which hardware threads to activate or deactivate based on partition scheduling requirements, without requiring external control from the partition manager. This self-service capability eliminates the overhead of external intervention while maintaining proper thread management.
2Productivity
If hardware threads are dynamically activated and inactivated to enhance processing capacity, then processor throughput is improved, but the complexity of thread scheduling and control increases
Solution Approach 1:
The patent merges the thread scheduling function with the partition scheduling function in the scheduler. Instead of having separate mechanisms for partition management and thread management, the scheduler integrates both functionalities, using the partition schedule to directly control hardware thread activation. This integration simplifies the overall control structure while maintaining dynamic thread management capabilities.
Solution Approach 2:
The scheduler is designed to perform multiple functions: it manages both partition scheduling and hardware thread activation/deactivation. By making the scheduler universal, the system reduces the number of separate control components needed, thereby reducing overall system complexity while maintaining the ability to dynamically adjust processing capacity.
3Reliability
If the partition manager controls hardware thread state transitions, then partition resource management is maintained, but switching overhead prevents real-time performance
Solution Approach 1:
The patent extracts the thread state control authority from the partition manager and transfers it to the local scheduler. The scheduler can now directly activate or deactivate hardware threads based on partition scheduling decisions without requiring partition manager intervention. This extraction eliminates the time-consuming communication and control overhead associated with partition manager involvement in thread state transitions.
Solution Approach 2:
The scheduler proactively manages hardware thread activation and deactivation in advance based on partition schedule requirements. By anticipating when threads need to be activated or deactivated, the scheduler can prepare and execute these transitions without waiting for partition manager commands, thereby reducing switching overhead and improving real-time performance.
Data Source
AI summary
A semiconductor device includes an execution unit that executes an arithmetic instruction, and a scheduler including multiple first setting registers each defining a correspondence relationship between hardware threads and partitions, and which generates a thread select signal on the basis of a partition schedule and a thread schedule. The scheduler outputs a thread select signal designating a specific hardware thread, without depending on the thread schedule as the partition indicated by a first occupation control signal, according to a first occupation control signal output when the execution unit executes a first occupation start instruction.