Thread Scheduler Power Manager State Awareness

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Solution Overview

Problem

Traditional thread scheduling in computing systems does not consider detailed performance and idle state information of processors, leading to inefficient decisions regarding power and performance.

Innovation Solution

Implementing a thread scheduler that communicates with a power manager to utilize multi-level idle and performance state information of processors, applying weighted factors to select processors based on exit latencies and power savings, and prioritizing threads accordingly to optimize energy efficiency and responsiveness.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If the processor enters deep idle states to save power, then energy efficiency is improved, but exit latency increases causing slower response to scheduling requests

Engineering Contradiction:
Improveenergy efficiencyVSAvoidexit latency
Core Design Contradiction:
Use of energy by moving objectVSLoss of time

Solution Approach 1:

The power manager proactively monitors processor state and preemptively wakes up processors from idle states before the scheduler needs to assign tasks, ensuring processors are ready for immediate task execution without incurring latency penalties when scheduling occurs

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system continuously monitors processor idle states, exit latencies, and scheduling patterns, using this feedback to dynamically adjust power management decisions and scheduling policies to balance energy efficiency with responsiveness

Inventive Principle:
Principle #23Feedback

2Ease of operation

If the scheduler selects processors without considering their current performance and idle states, then scheduling simplicity is maintained, but system performance and energy efficiency deteriorate

Engineering Contradiction:
Improvescheduling simplicityVSAvoidsystem performance
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

A power manager intermediary component is introduced between the scheduler and processors. This intermediary handles the complexity of monitoring processor states, calculating metrics, and making informed recommendations, allowing the scheduler to make simple selection decisions while the intermediary manages the complex state tracking and analysis

Inventive Principle:
Principle #24Intermediary (Mediator)

3Measurement precision

If the system tracks detailed multi-level performance and idle state information, then scheduling decision quality is improved, but system complexity increases

Engineering Contradiction:
Improvestate information accuracyVSAvoidsystem complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The system segments the complex state tracking into distinct components: the power manager handles processor state monitoring and metric calculation, while the scheduler handles task assignment. This segmentation allows detailed tracking without overwhelming the scheduling logic with complexity

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The power manager acts as an intermediary that abstracts the complexity of multi-level state tracking. It collects detailed information about processor performance states and idle states, processes this information to calculate relevant metrics, and presents simplified recommendations to the scheduler, thereby managing complexity while maintaining measurement precision

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentEP3278220B1Power aware scheduling and power manager
Publication Date: 2022.08.03 MICROSOFT TECHNOLOGY LICENSING LLC
  • EP3278220B1 patent drawingFigure 1
  • EP3278220B1 patent drawingFigure 2

AI summary

A computing system having a plurality of processing units configured to perform work by having threads assigned to the processing units. A thread scheduler is coupled to the plurality of processors and configured to schedule threads to the processing units. A power manager is coupled to the thread scheduler and controls performance states or idle states of the processing units. The thread scheduler maintains information about current performance state or idle state per processing unit. The information includes a multi-level description of the processing units in the computing system. The multi-level description includes three or more different entry values of different levels for performance state or idle state for processing units. The power manager provides the multi-level description of the processing units to the thread scheduler, which is configured to schedule threads to the processing units based on the multi-level description.