Thread Scheduler Core Utilization Redistribution

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Solution Overview

Problem

In multi-processor systems, the operating system lacks the ability to distinguish between individual processors on separate sockets, leading to inefficient thread allocation and execution, where one processor may be fully utilized while another is idle due to inadequate frequency adjustment based on workload.

Innovation Solution

A method where a thread scheduler determines core utilization rates and re-assigns threads from a heavily utilized processor to a less loaded one, allowing for optimal execution across multiple processors, thereby improving overall processing speed and efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If the operating system treats all logical processors across all sockets as one large contiguous bank, then thread allocation is simplified, but processor utilization becomes inefficient with some processors idle while others are fully utilized

Engineering Contradiction:
Improvethread allocation complexityVSAvoidprocessor utilization efficiency
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent segments the contiguous bank of logical processors into distinct processor groups corresponding to individual physical processors or sockets. This segmentation enables the thread scheduler to make informed decisions about thread placement based on per-processor utilization states, thereby improving processor utilization efficiency while maintaining manageable allocation complexity through structured grouping.

Inventive Principle:
Principle #1Segmentation

2Ease of operation

If threads are assigned to processors without considering individual processor utilization states, then thread scheduling is simplified, but execution speed decreases due to processors operating at low frequencies under heavy load

Engineering Contradiction:
Improvethread scheduling simplicityVSAvoidthread execution speed
Core Design Contradiction:
Ease of operationVSSpeed

Solution Approach 1:

The patent implements feedback mechanisms where the thread scheduler monitors processor utilization states and adjusts thread assignment decisions accordingly. This feedback loop enables the scheduler to migrate threads from overloaded processors to underutilized ones, thereby improving thread execution speed while maintaining relatively simple scheduling operations through automated load balancing.

Inventive Principle:
Principle #23Feedback

3Power

If processors operate at high frequencies with many cores utilized, then processing power increases, but power consumption and heat generation increase

Engineering Contradiction:
Improveprocessing powerVSAvoidpower consumption
Core Design Contradiction:
PowerVSUse of energy by moving object

Solution Approach 1:

The patent dynamically adjusts processor frequency and core utilization based on actual workload demands. By monitoring thread execution patterns and processor utilization states, the system can dynamically throttle frequencies or deactivate cores when full utilization is not required, thereby reducing power consumption while maintaining processing power when needed through selective core activation and frequency adjustment.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS9715415B2Method of scheduling threads for execution on multiple processors within an information handling system
Publication Date: 2017.07.25 DELL PROD LP
  • US9715415B2 patent drawing
  • US9715415B2 patent drawing
  • US9715415B2 patent drawing

AI summary

A method for improving thread execution speed within a multi-processor system includes a first processor and a second processor. The first processor generates threads to schedule for execution on the processors and initially assigns at least one thread to the first processor for execution on a core of the first processor. The first processor determines a core utilization rate for each of the threads and identifies whether the threads being scheduled have a core utilization rate greater than a pre-established core utilization rate threshold. In response to identifying a specific thread executing on the first processor that has a core utilization rate that is greater than the pre-established core utilization rate threshold, the first processor re-assigns execution of the specific thread from the first processor to the second processor. The re-assigned thread executes on the second processor at a greater execution rate than the pre-established core utilization rate threshold.