Thread Scheduling via Hardware Sharing Hierarchy
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Solution Overview
Problem
The complexity of modern multiprocessor systems with multiple processing units and shared hardware components leads to performance issues due to contention over shared resources, necessitating improved techniques for managing software threads and hardware components.
Innovation Solution
A computer-based mechanism that creates a hierarchical graph structure representing hardware sharing relationships between processing units, allowing for load balancing and thread scheduling based on affinity and resource availability, to optimize resource allocation and reduce contention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple processing units and shared hardware components are used to increase computing power, then system productivity is improved, but device complexity increases and contention over shared resources occurs
Solution Approach 1:
The patent segments the multiprocessor system into processing units and hardware components, creating a hierarchical graph structure that represents sharing relationships. This segmentation allows the operating system to manage complexity by breaking down the system into manageable units with defined relationships, enabling controlled access and allocation of shared resources.
Solution Approach 2:
The patent introduces a hierarchical graph structure as an intermediary between the operating system and the physical hardware components. This graph acts as a mediator that abstracts the complex sharing relationships, allowing the OS to make scheduling decisions without directly managing the intricate web of shared resources between multiple processing units.
2Ease of operation
If processor sets abstraction is used to manage resource allocation, then ease of operation is improved, but adaptability to variations in multiprocessor architecture is limited
Solution Approach 1:
The patent implements a dynamic hierarchical graph structure that can adapt to different multiprocessor architectures. The graph is constructed based on actual hardware sharing relationships, allowing the system to dynamically adjust to variations in architecture. This dynamic approach enables the same resource management mechanisms to work across different processor configurations without requiring architecture-specific implementations.
Solution Approach 2:
The hierarchical graph structure serves as a universal abstraction that can represent various multiprocessor architectures. By using a unified graph-based model that can capture different sharing relationships (processor-to-processor, processor-to-component, component-to-component), the system achieves architecture independence while maintaining ease of operation through consistent resource management interfaces.
3Productivity
If threads are assigned to processing units without considering hardware sharing relationships, then scheduling simplicity is maintained, but contention over shared resources increases
Solution Approach 1:
The patent incorporates feedback mechanisms where the hierarchical graph structure provides information about hardware sharing relationships to the thread scheduling decisions. The system uses this feedback to identify potential contention scenarios and adjust thread assignments accordingly, placing threads on processing units that minimize shared resource conflicts while maximizing resource utilization.
Solution Approach 2:
The patent performs preliminary construction of the hierarchical graph structure that encodes hardware sharing relationships before thread scheduling begins. This preliminary action allows the system to pre-identify potential contention points and plan thread assignments that avoid these conflicts, rather than reacting to contention after it occurs. The graph structure is built in advance to guide intelligent scheduling decisions.
Data Source
AI summary
A device, system, and method are directed towards managing threads and components in computer system with one or more processing units. A processor group has an associated hierarchical structure containing nodes that may correspond to processing units, hardware components, or abstractions. The processor group hierarchy may be used to assign one or more threads to one or more processing units, by traversing the hierarchy based on various factors. The factor may include load balancing, affinity, sharing of components, loads, capacities, or other characteristics of components or threads. A processor group hierarchy may be used in conjunction with a designated processor set.