Thread Scheduling Algorithm for Heterogeneous Processor Modules

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Solution Overview

Problem

Current operating system software is optimized for homogeneous systems-on-a-chip (SoCs) and fails to effectively manage thread scheduling in heterogeneous topologies, which are common in modern systems, leading to suboptimal performance and energy efficiency due to the lack of consideration for diverse hardware topologies and feedback mechanisms.

Innovation Solution

The proposed solution involves a thread scheduling algorithm that considers the heterogeneous module topology and hardware feedback to optimize thread allocation across diverse processors, prioritizing performance or energy efficiency based on thread quality, priority, and expected runtime, using hardware-guided scheduling enhancements to select the most suitable module for each thread.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If operating system software is optimized for homogeneous topologies, then software compatibility and ease of implementation are improved, but performance and energy efficiency on heterogeneous systems deteriorate

Engineering Contradiction:
Improvesoftware compatibilityVSAvoidperformance on heterogeneous systems
Core Design Contradiction:
Ease of manufactureVSProductivity

Solution Approach 1:

The scheduler dynamically adapts its behavior based on the detected hardware topology. It transitions from static homogeneous scheduling to dynamic heterogeneous scheduling by identifying available modules (cores, clusters, big.LITTLE configurations) and adjusting scheduling policies in real-time to match the actual hardware architecture, thereby optimizing performance without sacrificing compatibility

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes scheduling parameters based on detected hardware characteristics. By monitoring hardware feedback and topology information, the scheduler modifies scheduling parameters such as thread placement, module selection, and resource allocation to suit heterogeneous configurations, enabling optimal performance across diverse hardware platforms

Inventive Principle:
Principle #35Parameter changes

2Device complexity

If thread scheduling ignores hardware topology and feedback, then system complexity is reduced, but performance optimization and energy efficiency deteriorate

Engineering Contradiction:
Improvescheduling system complexityVSAvoidperformance optimization
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The scheduler implements hardware feedback mechanisms that continuously monitor system state, module availability, and performance metrics. This feedback loop enables the scheduler to make informed decisions about thread placement and module selection, optimizing performance and energy efficiency while maintaining manageable complexity through automated adaptation

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The scheduling system performs self-configuration by automatically detecting hardware topology and adapting its behavior without requiring manual intervention or complex configuration. The system serves itself by autonomously optimizing thread scheduling based on real-time hardware feedback, reducing the burden on system administrators while achieving performance optimization

Inventive Principle:
Principle #25Self-service

3Speed

If threads are scheduled without considering module capabilities, then scheduling speed is improved, but system performance and energy efficiency deteriorate

Engineering Contradiction:
Improvescheduling speedVSAvoidsystem performance
Core Design Contradiction:
SpeedVSProductivity

Solution Approach 1:

The scheduler performs preliminary actions by pre-detecting and caching hardware topology information and module capabilities before thread scheduling begins. This advance preparation enables rapid scheduling decisions without real-time performance penalties, as the system has already gathered and processed hardware characterization data in advance

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20240264861A1Apparatus, method, and system for scheduling threads on a processor
Publication Date: 2024.08.08 INTEL CORP
  • US20240264861A1 patent drawing
  • US20240264861A1 patent drawing
  • US20240264861A1 patent drawing

AI summary

An apparatus, computer-implemented method, and system to schedule ready threads on a processor circuitry. T The apparatus includes memory circuitry, machine-readable instructions, and processor circuitry to determine a quality of a first thread of a set of threads that are ready for scheduling on the processor circuitry. Based on the quality of the first thread, the apparatus finds a set of modules of the processor circuitry that are available for scheduling. The apparatus further selects a preferred module of the set of modules for the first thread. The apparatus then schedules the first thread to run on the preferred module.