Thread Scheduling Logic for Multithreaded Processor Pipelines
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In computer systems, the increasing gap between processor speed and memory access speed leads to significant idle time due to cache misses and latency, necessitating an efficient method to schedule thread execution on shared microprocessor cores to maximize multithreaded processor performance.
Innovation Solution
A method and system that prioritize thread execution using a 'least recently executed' policy, tracking thread status in registers and using thread selection logic to sort threads for execution, accounting for idle, ready, speculative, and wait states to ensure fair and efficient scheduling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If hardware multithreading is implemented to reduce stalling and idle time, then processor utilization is improved, but device complexity increases due to replication of architected registers and thread management overhead
Solution Approach 1:
The patent segments the thread scheduling problem into distinct phases: identifying stalled threads, selecting ready threads from a pool, and managing thread states. This segmentation allows complex multithreaded operations to be broken down into manageable components, reducing overall system complexity while maintaining high processor utilization.
Solution Approach 2:
The patent implements dynamic thread state management where threads can transition between different states (stalled, ready, running) based on real-time conditions. This dynamic approach allows the processor to adaptively switch between threads, optimizing utilization without requiring static, complex scheduling structures.
2Loss of time
If multiple threads are scheduled on a shared pipeline, then idle time is reduced, but ensuring fair and correct scheduling becomes more difficult
Solution Approach 1:
The patent employs feedback mechanisms where the processor monitors thread execution states and adjusts scheduling decisions based on observed performance and stall patterns. This feedback loop ensures fair scheduling by continuously adapting to thread readiness and stall conditions, making scheduling correctness detectable and measurable through performance metrics.
Solution Approach 2:
The patent prepares thread state information and readiness indicators in advance, allowing the scheduler to make informed decisions without complex real-time analysis. By pre-computing thread readiness and maintaining organized thread state data, the system reduces scheduling difficulty while minimizing idle time.
3Measurement precision
If thread status tracking is implemented with multiple states, then scheduling accuracy is improved, but register usage and resource overhead increase
Solution Approach 1:
The patent designs thread status registers and selection logic that serve multiple functions: tracking thread states, identifying stalled threads, and selecting ready threads for execution. This multi-functionality reduces the total number of registers needed while maintaining high measurement precision for thread state tracking.
Solution Approach 2:
The patent combines thread state tracking and selection logic into integrated hardware structures that operate simultaneously. By merging these functions into unified components, the patent reduces resource overhead while maintaining accurate thread state information for precise scheduling decisions.
Data Source
AI summary
An apparatus and method for scheduling execution of multiple threads on a shared processor resource is described in connection with a multithreaded multiprocessor chip. Using a thread selection policy that switches between available threads every cycle to give priority to the least recently executed or scheduled threads, different threads are able to operate in a way that ensures no deadlocks or livelocks while maximizing aggregate performance and fairness between threads. Prioritization is accomplished by monitoring and sorting thread status information for each thread, including speculative states in which a thread may be speculatively scheduled, thereby improving usage of the execution pipeline by switching a thread in with a lower priority.