Thread Scheduling for Timing Window Detection

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Solution Overview

Problem

Timing window problems in complex symmetric multiprocessing (SMP) environments are difficult to detect due to their rarity and dependence on specific thread execution patterns, often leading to accidental introduction and challenging debugging processes.

Innovation Solution

A method and system that identify execution speeds for multiple threads and select CPU cores based on clock rate and execution speed to iterate through various thread-core mappings, triggering and detecting timing window problems by scheduling threads on specific CPU cores and controlling clock rates to reproduce rare execution scenarios.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If multithreaded execution is implemented to improve application performance, then execution speed is improved, but timing window problems (race conditions) may occur leading to reliability deterioration

Engineering Contradiction:
Improveexecution speedVSAvoidreliability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent applies preliminary action by performing static analysis of thread code before execution to identify potential timing window problems. The system analyzes thread instructions, identifies shared resources, and determines critical sections in advance, allowing preventive measures to be taken before race conditions actually occur during multithreaded execution.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback mechanisms by monitoring thread execution and detecting timing window problems in real-time. When a potential race condition is identified during execution, the system provides feedback to adjust scheduling decisions, modify thread behavior, or trigger corrective actions to maintain reliability while preserving multithreading performance benefits.

Inventive Principle:
Principle #23Feedback

2Ease of operation

If thread scheduling is left to the operating system to improve ease of operation, then ease of operation is improved, but detection of timing window problems becomes more difficult

Engineering Contradiction:
Improveease of operationVSAvoiddifficulty of detecting timing window problems
Core Design Contradiction:
Ease of operationVSDifficulty of detecting and measuring

Solution Approach 1:

The patent introduces an intermediary component that sits between the operating system scheduler and the thread execution. This intermediary performs static analysis and generates scheduling hints without replacing the OS scheduler, maintaining ease of operation while enabling detection of timing window problems through code analysis and monitoring of thread interactions.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Speed

If CPU clock rate is increased to improve execution speed, then execution speed is improved, but timing window problems become more likely to occur

Engineering Contradiction:
Improveexecution speedVSAvoidtiming window problems
Core Design Contradiction:
SpeedVSObject-affected harmful factors

Solution Approach 1:

The patent applies preliminary anti-action by identifying and protecting against timing window problems before they can be exploited by high clock rates. Through static analysis of thread code and identification of critical sections, the system prepares preventive measures that counteract the increased risk of race conditions caused by faster CPU execution, allowing high clock rates to be maintained safely.

Inventive Principle:
Principle #9Preliminary anti-action

Data Source

PatentUS11263114B2Method and technique to find timing window problems
Publication Date: 2022.03.01 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US11263114B2 patent drawing
  • US11263114B2 patent drawing
  • US11263114B2 patent drawing

AI summary

Threads of a multithreaded application may be scheduled to different cores and executed in various orders and at various frequencies. Controlling how the threads are scheduled and clock rates of processor cores enables testing multiple possible execution scenarios, which may force previously unknown timing window problems to occur. These timing window problems may then be detected.