Thread-Specific Indexing for Shared Storage Contention

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Solution Overview

Problem

Contention for shared storage structure entries between different threads in data processing systems can lead to performance degradation and increased vulnerability to side-channel attacks, as a malicious thread can infer access patterns from performance losses.

Innovation Solution

Incorporating indexing circuitry that generates a target index value as a function of the requested index value and a thread-specific key value, which is updated periodically or based on performance metrics, to ensure each thread uses a unique indexing scheme, reducing contention and masking access patterns.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If multiple threads share the same storage structure with identical indexing schemes, then device complexity is reduced, but thread contention increases leading to performance degradation

Engineering Contradiction:
Improveindexing scheme complexityVSAvoidthread access performance
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent applies local quality by assigning different key values to different threads, creating thread-specific indexing schemes. Each thread experiences a unique permutation of storage structure indices, so while the overall system uses a single shared storage structure (maintaining low device complexity), each thread effectively sees a customized indexing pattern that eliminates contention with other threads.

Inventive Principle:
Principle #3Local quality

2Ease of operation

If multiple threads use the same indexing scheme for shared storage, then ease of operation is improved, but vulnerability to side-channel attacks increases

Engineering Contradiction:
Improveindexing operation simplicityVSAvoidside-channel attack vulnerability
Core Design Contradiction:
Ease of operationVSObject-affected harmful factors

Solution Approach 1:

By applying local quality through thread-specific key values, the patent creates unique indexing schemes for each thread. This maintains operational simplicity from the system's perspective (a single storage structure is shared) while providing security through differentiation. The unique permutations make it difficult for malicious threads to infer access patterns of other threads, as the mapping between requested indices and actual storage locations varies per thread.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent implements dynamics by periodically updating key values for threads. This dynamic change in indexing schemes over time further obscures access patterns, making side-channel attacks even more difficult. The system transitions from static identical indexing to dynamic unique indexing, where the indexing pattern can change based on updates to the key values associated with each thread.

Inventive Principle:
Principle #15Dynamics

3Manufacturing precision

If threads access storage structure entries using identical index values, then manufacturing precision of indexing logic is maintained, but adverse aliasing increases reducing performance

Engineering Contradiction:
Improveindexing logic consistencyVSAvoidstorage access efficiency
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The patent applies parameter changes by modifying the indexing parameter (the key value) for each thread. This creates different effective index mappings without changing the fundamental indexing logic structure. The consistent application of the indexing function with different key parameters maintains manufacturing precision while the parameter variation eliminates adverse aliasing by ensuring that different threads map to different storage locations.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10725992B2Indexing entries of a storage structure shared between multiple threads
Publication Date: 2020.07.28 ARM LTD
  • US10725992B2 patent drawing
  • US10725992B2 patent drawing
  • US10725992B2 patent drawing

AI summary

An apparatus has processing circuitry for processing instructions from multiple threads. A storage structure is shared between the threads and has a number of entries. Indexing circuitry generates a target index value identifying an entry of the storage structure to be accessed in response to a request from the processing circuitry specifying a requested index value corresponding to information to be accessed from the storage structure. The indexing circuitry generates the target index value as a function of the requested index value and a key value selected depending on which of the threads trigger the request. The key value for at least one of the threads is updated from time to time.