Microprocessor Thread Switch Completion Continue Mechanism

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Solution Overview

Problem

Multithreaded processors face significant execution penalties and increased power dissipation due to the existing method of switching between threads, which involves flushing and re-fetching instructions, leading to duplicate execution of completed but uncommitted instructions.

Innovation Solution

A completion continue on thread switch mechanism is introduced, where an instruction progress metric is initiated during a context switch event, allowing the completion of backend pipeline instructions until expiry, and then flushing them, while pre-fetching instructions for the new thread at the frontend, reducing processing time and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the processor flushes the data pipeline and terminates uncommitted instructions during thread switching, then thread switching can be completed, but execution penalty increases due to re-fetching and duplicate execution

Engineering Contradiction:
Improvethread switching completionVSAvoidexecution penalty
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by initiating the instruction progress metric and preparing for thread switching before the actual switch occurs. The system pre-calculates which instructions can be safely completed and which must be flushed, allowing the backend to finish eligible instructions in advance rather than flushing everything immediately, thus reducing the execution penalty while ensuring thread switching completion

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent segments the pipeline into frontend and backend portions, applying different thread switching strategies to each. The frontend flushes instructions to ensure clean state for the new thread, while the backend completes instructions that have already been dispatched. This segmentation allows simultaneous execution of flush operations and completion operations, reducing overall switching time

Inventive Principle:
Principle #1Segmentation

2Reliability

If the processor flushes and re-fetches instructions during thread switching, then thread context can be switched, but power dissipation increases

Engineering Contradiction:
Improvethread context switchingVSAvoidpower dissipation
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent applies discarding and recovering by identifying instructions that have been completed but not yet committed, discarding the need to re-fetch them, and recovering the energy that would have been spent on duplicate execution. The instruction progress metric tracks which instructions can be safely discarded without re-fetching, directly reducing power dissipation during thread switching

Inventive Principle:
Principle #34Discarding and recovering

3Loss of time

If the processor completes backend instructions until expiry of instruction progress metric, then execution time is reduced, but device complexity increases

Engineering Contradiction:
Improveexecution timeVSAvoidthread management complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent implements feedback through the instruction progress metric, which continuously monitors instruction completion status and provides feedback to the thread switching mechanism. The metric expires based on predefined criteria, providing automatic feedback that triggers the flush operation. This feedback mechanism automates the decision-making process, reducing the need for complex manual thread management while minimizing execution time

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS7941646B2Completion continue on thread switch based on instruction progress metric mechanism for a microprocessor
Publication Date: 2011.05.10 NXP USA INC
  • US7941646B2 patent drawing
  • US7941646B2 patent drawing
  • US7941646B2 patent drawing

AI summary

A thread switch mechanism and technique for a microprocessor is disclosed wherein a processing of a first thread is completed, and a continuation of a second thread is initiated during completion of the first thread. In one form, the technique includes processing a first thread at a pipeline of a processing device, and initiating processing of a second thread at a front end of the pipeline in response to an occurrence of a context switch event. The technique can also include initiating a instruction progress metric in response the context switch event. The technique can further include enabling completion of processing of instructions of the first thread that are at a back end of the pipeline at the occurrence of the context switch event until an expiry of the instruction progress metric.