Program Thread Synchronization via Cache Line Invalidation
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Solution Overview
Problem
Conventional synchronization techniques in multiprocessor systems face challenges with shared counters becoming 'hot spots' leading to contention and increased time for thread synchronization, while specialized hardware complicates system design and reduces flexibility.
Innovation Solution
A method and system that utilize a barrier filter to stall and resume program threads by invalidating and validating data cache lines, with a memory fence to prevent speculative execution, allowing quick synchronization without shared counters or complex hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a shared counter is used for synchronization, then threads can be synchronized at a barrier, but the counter becomes a hot spot causing contention and increasing synchronization time
Solution Approach 1:
The patent extracts the synchronization state from a shared counter and embeds it directly into individual cache lines. Each thread has its own cache line copy, eliminating the need for a centralized counter that causes contention. Threads check their local cache line state rather than contending for a shared resource, thus resolving the hot spot problem while maintaining synchronization correctness.
Solution Approach 2:
The patent segments the centralized counter into distributed cache line copies, with each thread having its own local copy in its cache. This segmentation allows parallel access without contention, as each thread operates on its own segment rather than competing for a single shared counter.
2Object-generated harmful factors
If threads test the counter less often to reduce contention, then contention is lessened, but the time required for threads to learn when the barrier has been reached increases
Solution Approach 1:
The patent enables continuous monitoring of barrier state by having threads check their local cache line state frequently without causing contention. Since each thread has its own cache line copy, frequent checks do not create the hot spot problem, allowing threads to detect barrier completion quickly while maintaining low contention levels.
3Reliability
If specialized hardware is used for synchronization, then synchronization can be implemented, but the design and manufacture of the multiprocessor system becomes complicated and flexibility is limited
Solution Approach 1:
The patent makes the cache system self-service for synchronization purposes. The cache coherence protocol that already exists in the system is leveraged to provide barrier synchronization functionality without requiring specialized hardware. The existing cache infrastructure serves dual purposes: data storage and synchronization state management, eliminating the need for additional specialized synchronization hardware.
Solution Approach 2:
The patent makes the cache lines multi-functional, serving both as data storage and as synchronization state indicators. The same cache infrastructure that stores program data is also used to signal barrier completion, eliminating the need for separate specialized synchronization hardware and reducing system complexity.
Data Source
AI summary
The present invention is a method of and system for program thread synchronization. In accordance with an embodiment of the invention, a method of synchronizing program threads for one or more processors is provided. An address for data for each of a plurality of program threads to be synchronized is determined. For each processor executing one or more of the threads to be synchronized, execution of the thread is halted at a barrier by attempting a data operation to the determined address and the address being unavailable. Execution of the threads is resumed.