Thread Synchronization via Virtual Memory Protection
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Solution Overview
Problem
Conventional synchronization approaches in computer systems, such as the atomic instruction and simple load-store methods, are inefficient due to the high latency of instructions like CAS and MEMBAR, which can lead to exclusion failures and significant cycle overhead, especially when multiple threads frequently access shared resources.
Innovation Solution
A method that allows a first thread to request a lock on a shared resource and ensure the operations of a second thread are visible in the correct order, eliminating the need for MEMBAR instructions in the second thread by using a change virtual memory access protection system call, thereby reducing cycle overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If MEMBAR instructions are used to ensure correct visibility order of operations in load-store synchronization, then exclusion failure is prevented, but cycle overhead increases significantly
Solution Approach 1:
The patent extracts the memory ordering enforcement from the frequent thread and relocates it to the infrequent thread. By having the infrequent thread perform the visibility enforcement operation (analogous to MEMBAR) only when it attempts to access the shared resource, the system eliminates the need for continuous MEMBAR instructions in the frequent thread, thereby reducing cycle overhead while maintaining exclusion safety
Solution Approach 2:
The infrequent thread performs a preliminary visibility enforcement action before checking the lock status. This preliminary action ensures that when the infrequent thread reads the lock variable, it sees the most recent write by the frequent thread, establishing correct ordering without requiring the frequent thread to continuously enforce ordering
2Reliability
If atomic CAS instructions are used for synchronization, then mutual exclusion is achieved, but instruction latency increases
Solution Approach 1:
The patent uses simple load-store operations with software-managed locking variables instead of expensive atomic CAS instructions. The lock variables act as disposable synchronization primitives that can be freely written and read without requiring complex atomic hardware support, thereby reducing instruction latency while maintaining mutual exclusion through software protocols
Solution Approach 2:
The patent substitutes hardware-based atomic operations with software-based load-store sequences. By using ordinary memory operations combined with visibility enforcement and polling logic, the system replaces the mechanical CAS instruction with a software protocol that achieves the same synchronization goal with lower latency on architectures where store buffers and out-of-order execution are present
Data Source
AI summary
A technique for accessing a shared resource of a computerized system involves running a first portion of a first thread within the computerized system, the first portion (i) requesting a lock on the shared resource and (ii) directing the computerized system to make operations of a second thread visible in a correct order. The technique further involves making operations of the second thread visible in the correct order in response to the first portion of the first thread running within the computerized system, and running a second portion of the first thread within the computerized system to determine whether the first thread has obtained the lock on the shared resource. Such a technique alleviates the need for using a MEMBAR instruction in the second thread.