Thread Throttling for Shared Cache Contention

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Solution Overview

Problem

Resource contention in multi-threaded computing systems leads to performance degradation due to stalls when multiple computation units compete for shared resources, as existing methods fail to efficiently arbitrate threads and manage resource utilization effectively.

Innovation Solution

Implementing a thread throttling mechanism that monitors cache misses at the L2 cache level, setting thresholds for cache misses, and adjusting the severity level of throttling for upstream computation units to balance resource usage and maintain memory bandwidth, thereby reducing resource contention and performance penalties.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple threads are allowed to access shared resources simultaneously, then parallel execution capability is improved, but resource contention increases causing multi-cycle stalls

Engineering Contradiction:
Improveparallel execution capabilityVSAvoidmulti-cycle stall duration
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The system performs preliminary actions by monitoring cache miss counts and predicting future resource contention before it occurs. When a thread exceeds its cache miss threshold, the system proactively throttles that thread's instruction fetch rate upstream from the shared resource, preventing stalls before they impact overall productivity.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system dynamically adjusts the number of instructions fetched per cycle for each thread based on real-time cache miss monitoring. The instruction fetch rate is made variable rather than fixed, allowing the system to optimize parallel execution by reducing fetch rates for threads experiencing high cache miss rates while maintaining higher rates for threads with better cache performance.

Inventive Principle:
Principle #15Dynamics

2Device complexity

If thread arbitration is performed at the shared resource level, then resource access control is simplified, but upstream resources (instruction fetch unit, decode unit) are wasted during stalls

Engineering Contradiction:
Improvearbitration control complexityVSAvoidupstream resource utilization waste
Core Design Contradiction:
Device complexityVSLoss of energy

Solution Approach 1:

The system introduces an intermediary throttling mechanism between the upstream resources (instruction fetch unit, decode unit) and the shared resource (L2 cache). This intermediary layer monitors cache miss conditions and adjusts instruction fetch rates proactively, preventing upstream resources from being wasted during stalls by reducing fetch rates before threads reach the shared resource.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

Instead of waiting for stalls to occur at the shared resource level and then arbitrating, the system takes preliminary action by monitoring cache miss counts and throttling upstream instruction fetches in advance. This prevents the waste of upstream resources during stalls by reducing the number of instructions that reach the shared resource in the first place.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If cache miss threshold is set low, then resource contention is detected early, but normal operation may be incorrectly throttled

Engineering Contradiction:
Improveresource contention detection accuracyVSAvoidfalse throttling of normal operations
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system applies local quality by setting thread-specific cache miss thresholds rather than using a single global threshold. Each thread is assigned a threshold based on its workload characteristics and importance, allowing early detection of contention for critical threads while being more tolerant of cache misses for less critical threads, thus reducing false throttling.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The system changes the parameter of cache miss threshold dynamically or per-thread rather than using a fixed universal value. By adjusting this parameter based on thread-specific characteristics and current system conditions, the system can reliably detect genuine resource contention while avoiding the throttling of normal operational cache misses.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentEP4034993B1Throttling while managing upstream resources
Publication Date: 2024.04.17 ONESTA IP LLC
  • EP4034993B1 patent drawingFigure 1
  • EP4034993B1 patent drawingFigure 2
  • EP4034993B1 patent drawingFigure 3

AI summary

Systems, apparatuses, and methods for arbitrating threads in a computing system are disclosed. A computing system includes a processor with multiple cores, each capable of simultaneously processing instructions of multiple threads. When a thread throttling unit receives an indication that a shared cache has resource contention, the throttling unit sets a threshold number of cache misses for the cache. If the number of cache misses exceeds this threshold, then the throttling unit notifies a particular upstream computation unit to throttle the processing of instructions for the thread. After a time period elapses, if the cache continues to exceed the threshold, then the throttling unit notifies the upstream computation unit to more restrictively throttle the thread by performing one or more of reducing the selection rate and increasing the time period. Otherwise, the unit notifies the upstream computation unit to less restrictively throttle the thread.