Threaded Memory Transactions With Asymmetric Bus Rates
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Solution Overview
Problem
Conventional buffered memory systems often suffer from unused bandwidth due to primary and secondary buses being locked to the same transfer rate, which can lead to inefficiencies and higher costs when using high-capacity memory modules.
Innovation Solution
Implementing a memory system where the primary signaling interface operates at a rate at least twice the secondary signaling rate, allowing data transfers to overlap and optimize bandwidth utilization, thereby enabling the use of less expensive memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If primary and secondary buses are locked to the same transfer rate, then data transfer reliability is maintained, but bandwidth utilization deteriorates
Solution Approach 1:
The patent applies dynamics by allowing the primary bus to operate at a higher transfer rate than the secondary bus, creating an asymmetric rate configuration. This enables the system to adapt to different performance requirements at different stages of data transfer, optimizing bandwidth utilization while maintaining reliability through the buffer's ability to absorb rate differences.
Solution Approach 2:
The patent changes the parameter of transfer rate by establishing that the primary bus operates at a rate at least twice the secondary bus rate. This parameter change allows the system to optimize bandwidth efficiency by matching the faster primary bus rate with higher-performance memory devices while using the slower secondary bus rate for connection to memory devices, thereby resolving the contradiction between bandwidth utilization and reliability.
2Productivity
If primary bus operates at higher transfer rate than secondary bus, then bandwidth efficiency is improved, but system complexity increases
Solution Approach 1:
The buffer circuitry serves as an intermediary element between the primary bus and secondary bus, absorbing the complexity of rate differences. By positioning the buffer at the interface between the two buses with different rates, the system can achieve high bandwidth efficiency without proportionally increasing overall system complexity, as the buffer manages the rate mismatch automatically.
3Speed
If faster memory devices are used, then data transfer speed is improved, but hardware cost increases
Solution Approach 1:
The patent applies local quality by assigning different performance characteristics to different parts of the system: the primary bus and memory controller interface operate at high speed to match expensive fast memory devices, while the secondary bus operates at a lower speed. This allows the system to invest in high-speed components only where necessary, reducing overall hardware cost while maintaining optimal performance at the critical interface.
Data Source
AI summary
Memory modules, systems, memory controllers and associated methods are disclosed. In one embodiment, a memory module includes a module substrate having first and second memory devices. Buffer circuitry disposed on the substrate couples to the first and second memory devices via respective first and second secondary interfaces. The buffer circuitry includes a primary signaling interface for coupling to a group of signaling links associated with a memory controller. The primary signaling interface operates at a primary signaling rate and the first and second secondary data interfaces operate at a secondary signaling rate. During a first mode of operation, the primary interface signaling rate is at least twice the secondary signaling rate. A first time interval associated with a transfer of first column data via the first secondary interface temporally overlaps a second time interval involving second column data transferred via the second secondary interface.