Threaded Memory Signal Synchronization via Delay Calibration
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Solution Overview
Problem
In memory systems using fly-by addressing and module threading, synchronizing shared address signals with per-thread control signals is challenging due to timing differences, which can affect signal integrity and data rates, especially as data rates increase.
Innovation Solution
The synchronization is achieved through physical trace-length matching, controller-based delay delta calibration, and using pre-computed delay deltas stored in non-volatile memory, ensuring that address and control signals arrive simultaneously at memory devices, thereby maintaining signal integrity and optimizing data rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If fly-by addressing and module threading are used to increase data rates and bandwidth, then productivity is improved, but timing synchronization between address and control signals deteriorates
Solution Approach 1:
The patent applies preliminary action by pre-computing delay deltas during manufacturing and storing them in non-volatile memory on the memory module. These pre-calculated timing compensation values are then used during operation to synchronize control signals with address signals, eliminating the need for complex real-time calibration and maintaining synchronization precision at high data rates.
Solution Approach 2:
The patent replaces physical trace-length matching (mechanical adjustment) with electronic delay compensation using pre-computed values stored in non-volatile memory. This substitution allows for more precise and flexible timing synchronization without the limitations of physical routing adjustments, enabling maintained signal integrity at higher data rates.
2Adaptability or versatility
If per-thread control signals are used to enable independent memory device subset accesses, then adaptability is improved, but signal timing alignment with address signals deteriorates
Solution Approach 1:
The patent applies segmentation by dividing the memory devices into multiple subsets, each controlled by its own per-thread control signal. This allows independent access to different memory subsets while the patent simultaneously provides timing synchronization for each segmented control signal group, ensuring that each subset can be independently accessed without timing conflicts.
Solution Approach 2:
The patent applies local quality by providing individualized delay delta calibration for each per-thread control signal based on its specific routing characteristics. Each control signal group receives customized timing compensation values that account for its local signal path characteristics, ensuring precise timing alignment despite the diversity of routing paths required for independent subset access.
3Manufacturing precision
If trace-length matching is used to synchronize signals, then timing synchronization is improved, but device complexity increases
Solution Approach 1:
The patent applies copying by storing pre-computed delay delta values in non-volatile memory on the memory module. Instead of physically matching trace lengths, the system copies the timing compensation information into electronic storage, which can then be retrieved and applied during operation. This reduces the complexity of physical signal routing while maintaining precise timing synchronization.
4Manufacturing precision
If delay delta calibration is performed to compensate for timing differences, then timing synchronization is improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary action by performing delay delta calibration during the manufacturing process and storing the results in non-volatile memory. This preliminary calibration eliminates the need for complex field adjustments or real-time calibration routines, simplifying both the manufacturing process and final system deployment while maintaining high timing synchronization precision.
Data Source
AI summary
A memory system includes a memory module which further includes a set of memory devices. The set of memory devices includes a first subset of memory devices and a second subset of memory devices. An address bus is disposed on the memory module, wherein the address bus includes a first segment coupled to the first subset and a second segment coupled to the second subset. An address signal traverses the set of memory devices in sequence. The memory system also includes a memory controller which is coupled to the memory module. The memory controller includes a first circuit to output a first control signal that controls the first subset, such that the first control signal and the address signal arrive at a memory device in the first subset at substantially the same time. The memory controller additionally includes a second circuit to output a second control signal that controls the second subset, such that the second control signal and the address signal arrive at a memory device in the second subset at substantially the same time.