Memory Structure with Three-Bit-Line Groups for Two-Bit Storage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The storage density of mask type read-only memory is limited as each memory transistor can only store one bit of data, necessitating an improvement in storage capacity.
Innovation Solution
A memory structure is designed with a plurality of memory transistors arranged in an array, featuring bit line groups with multiple bit lines (first, second, and third bit lines) and connection pads, allowing each transistor to store two bits of data based on connection relationships with these bit lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If each memory transistor stores only one bit of data, then the memory structure is simple and reliable, but the storage density is limited
Solution Approach 1:
The patent introduces a third dimension by adding a third bit line alongside the first and second bit lines. This dimensional expansion allows the memory transistor to have multiple connection options (connected to first bit line, second bit line, third bit line, or none), enabling 2-bit storage capability without fundamentally changing the transistor structure itself.
Solution Approach 2:
The bit line group is segmented into multiple independent bit lines (first bit line, second bit line, third bit line) that can be independently connected to the memory transistor. This segmentation allows different connection configurations to represent different data states, achieving higher storage density while maintaining simple transistor architecture.
2Productivity
If multiple bit lines are added to enable 2-bit storage, then storage capacity improves, but the device complexity increases
Solution Approach 1:
The memory transistor structure remains universal and unchanged, but its functionality is enhanced through the multi-functional bit line group. The same transistor can store different data values (00, 01, 10, 11) by changing which bit line it connects to, making the system more versatile without adding complexity to the core storage element.
Solution Approach 2:
The third bit line is nested within the existing bit line group structure, extending along the same first direction and arranged along the third direction. This nested configuration allows the additional bit line to be integrated into the existing memory structure without requiring a complete redesign, thus improving capacity with minimal added complexity.
Data Source
AI summary
Implementations of the present disclosure provide a memory structure, a memory, and a memory system. The memory structure includes: a plurality of memory transistors arranged in an array along a first direction and a second direction; and a plurality of bit line groups extending along the first direction and arranged along the second direction, each of which includes a first, second, and third bit lines extending along the first direction and arranged along a third direction; wherein the memory transistor is connected to any one of the first, second, and third bit lines in the same bit line group, or the memory transistor is not connected to the first, second, and third bit lines in the same bit line group; the first direction intersects with the second direction, and both of the first and second directions are perpendicular to the third direction.