Three-Channel Cache Coherency Protocol for Reduced Logic Complexity
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Solution Overview
Problem
Existing cache coherency protocols in systems on chip require complex logic and numerous channels, leading to increased latency, design bugs, and reduced architectural performance due to complex dependencies and channel management.
Innovation Solution
A simplified cache coherency protocol utilizing just three channels (alpha, beta, and gamma) for information transfer between initiators and targets, eliminating the need for complex ordering rules and reducing logic requirements, thereby improving scalability and reducing the risk of design bugs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing cache coherency protocols are implemented with multiple channels and complex ordering rules, then cache coherency can be maintained, but logic complexity increases and maximum reachable frequency decreases
Solution Approach 1:
The protocol segments cache coherency operations into three distinct message classes (probe, acknowledgment, response) that are transmitted on separate virtual channels. This segmentation allows each channel to handle specific message types with simplified rules, eliminating the need for complex ordering logic while maintaining coherency guarantees.
Solution Approach 2:
The patent introduces a socket interface as an intermediary layer between the cache coherent agents and the network fabric. This socket absorbs and manages the complexity of channel coordination, presenting a simplified interface to higher-level protocols while handling the detailed channel management internally.
2Reliability
If existing cache coherency protocols are implemented with numerous channels, then cache coherency information can be exchanged, but the amount of logic required increases and design bugs become more likely
Solution Approach 1:
The three virtual channels are designed to be universal and reusable across different message types and transactions. Each channel handles a specific message class but can be used for multiple different cache coherency operations, reducing the total number of channels needed compared to protocols that dedicate separate channels to each operation type.
Solution Approach 2:
The patent merges multiple protocol functions into the three-channel framework. The same three channels handle probe messages, acknowledgment messages, and response messages for various cache coherency operations, consolidating what would otherwise require numerous separate channels in traditional protocols.
3Stability of the object's composition
If complex ordering rules are implemented in cache coherency protocols, then message ordering can be ensured, but channel management becomes more complex and architectural performance decreases
Solution Approach 1:
Each virtual channel is assigned a specific message class with localized ordering rules appropriate to that message type. Probe messages on one channel have different ordering requirements than acknowledgment messages on another channel, allowing each channel to be optimized independently rather than requiring a single complex global ordering mechanism.
Data Source
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AI summary
A system and method are disclosed for communicating coherency information between initiator and target agents on semiconductor chips. Sufficient information communication to support full coherency is performed through a socket interface using only three channels. Transaction requests are issued on one channel with responses given on a second. Intervention requests are issued on the same channel as transaction responses. Intervention responses are given on a third channel. Such an approach drastically reduces the complexity of cache coherent socket interfaces compared to conventional approaches. The net effect is faster logic, smaller silicon area, improved architecture performance, and a reduced probability of bugs by the designers of coherent initiators and targets.