Three-Dimensional Array Circuits With Overlapped Interlayer Connections
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Solution Overview
Problem
Existing three-dimensional neural networks face challenges in vertical integration due to the need for techniques like TSV or wire bonding, leading to increased signal delay and power consumption from long wiring lengths in stacked non-volatile memory chips for in-memory computing.
Innovation Solution
A three-dimensional array device with a stacked structure where two-dimensional array circuits are rotated 90 degrees relative to each other, minimizing wiring length by overlapping input and output parts, and using electrical connections such as vias or TSVs to reduce signal delay and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If three-dimensional neural networks use conventional stacking techniques like TSV or wire bonding, then vertical integration is achieved, but signal delay and power consumption increase due to long wiring lengths
Solution Approach 1:
The patent transitions from two-dimensional planar arrangements to three-dimensional stacked configurations, where array circuits are arranged in multiple layers vertically. This dimensional change allows signals to transfer between adjacent layers with minimal wiring length, reducing signal delay while achieving vertical integration for increased computational capacity
Solution Approach 2:
The patent combines multiple array circuits into a single three-dimensional stacked structure where output parts of lower-layer circuits are directly connected to input parts of upper-layer circuits. This merging eliminates the need for long external interconnects, reducing both signal delay and power consumption while maintaining integration
2Device complexity
If three-dimensional neural networks use conventional stacking techniques like TSV or wire bonding, then vertical integration is achieved, but power consumption increases due to long wiring lengths
Solution Approach 1:
By stacking array circuits vertically in three dimensions, the patent minimizes the physical distance signals must travel between layers. This reduces the energy required for signal transmission compared to conventional two-dimensional layouts or techniques requiring long TSV/wire bond interconnects, thereby reducing power consumption
Solution Approach 2:
The patent converts the potential harm of vertical stacking (which could increase complexity and power consumption) into a benefit by strategically positioning output and input parts to overlap in plan view. This arrangement ensures that signals transfer between adjacent layers with minimal wiring, transforming the three-dimensional structure into an energy-efficient configuration
3Area of stationary object
If two-dimensional array circuits are stacked without rotation, then area efficiency is maintained, but wiring length increases due to misalignment of input and output parts
Solution Approach 1:
The patent introduces asymmetry by rotating array circuits in alternating layers by 45 degrees relative to adjacent layers. This rotational offset creates a staggered configuration where output parts of lower layers align with input parts of upper layers, minimizing wiring length while maintaining compact three-dimensional stacking and area efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables a neural network with low latency and low energy loss by optimizing signal transfer through minimized wiring lengths, improving area-efficiency and reducing power consumption.
Implementation Method 1
Re RAM has a function of an element called a memristor in which the resistive value changes by storing the quantity of charges flowing through the element
Data Source
AI summary
A three-dimensional array device with multiple layers in height direction includes a first two-dimensional array circuit located in a first layer; and a second two-dimensional array circuit located in a second layer adjacent to the first layer and overlapped in a plan view with the first two-dimensional array circuit. Each of the first two-dimensional array circuit and the second two-dimensional array circuit has a first wiring group, an input part that inputs signals to the first wiring group, a second wiring group that intersects the first wiring group and an output part that outputs signals from the second wiring group. The output part in the first two-dimensional array circuit is overlapped in a plan view on the input part in the second two-dimensional array circuit and is connected in a signal transferable manner.