Three-Dimensional DRAM Manufacturing With Epitaxial Silicon Layers

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Solution Overview

Problem

Existing methods for manufacturing semiconductor memory devices face challenges in achieving high integration of memory cells, particularly in three-dimensional structures, which affect the efficiency and density of dynamic random access memory (DRAM) devices.

Innovation Solution

A method involving the formation of single crystal silicon layers and layers of different materials to create a three-dimensional structure with specific impurity regions and electrical connections, including the use of solid phase and vapor phase epitaxial growth methods to form single crystal silicon layers, and the integration of capacitors and gate electrodes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If memory cells are three-dimensionally disposed to realize high integration, then the integration density is improved, but the manufacturing complexity increases

Engineering Contradiction:
Improveintegration densityVSAvoidmanufacturing complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent transitions from planar two-dimensional memory cell arrangement to three-dimensional vertical stacking, where memory cells are disposed in multiple layers above the substrate. This dimensional change enables higher integration density by utilizing the vertical space rather than only horizontal plane, allowing more memory cells to be packed into the same footprint area.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The manufacturing process is divided into multiple discrete steps including forming insulating films, creating openings, depositing electrode materials, and patterning gate electrodes for each memory cell layer. This segmentation of the complex three-dimensional manufacturing into manageable sequential steps makes the high-density structure achievable through standardized repeated processes.

Inventive Principle:
Principle #1Segmentation

2Reliability

If single crystal silicon layers are formed using epitaxial growth methods, then the crystal quality is improved, but the manufacturing time increases

Engineering Contradiction:
Improvecrystal qualityVSAvoidmanufacturing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent employs both solid phase epitaxial growth and vapor phase epitaxial growth methods to form single crystal silicon layers. By changing the physical state and growth parameters between solid-phase and vapor-phase processes, the manufacturing time can be optimized while maintaining high crystal quality. The vapor phase method generally provides faster growth rates compared to solid phase, thus reducing manufacturing time while preserving reliability.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method enables the creation of a high-density, three-dimensional DRAM structure with improved crystal defect management, enhancing the performance and integration of memory cells, thereby improving the efficiency and capacity of semiconductor memory devices.

Implementation Method 1

the use of solid phase and vapor phase epitaxial growth methods to form single crystal silicon layers

Methodology Applied
Scientific EffectEpitaxial growth: Epitaxy

Data Source

PatentUS20250301737A1Method for manufacturing semiconductor memory device and semiconductor memory device
Publication Date: 2025.09.25 KIOXIA CORP
  • US20250301737A1 patent drawing
  • US20250301737A1 patent drawing
  • US20250301737A1 patent drawing

AI summary

A method for manufacturing a semiconductor memory device according to an embodiment includes: forming a first film, a second film, and a third film in a first direction of a single crystal silicon substrate; forming a first opening penetrating the third to first films reaching the single crystal silicon substrate; forming a first single crystal silicon layer in the first opening; forming a second opening penetrating the third and second films; etching the second film from a side face of the second opening to form a first recess reaching the first single crystal silicon layer; forming a second single crystal silicon layer in the first recess; forming a wiring layer in contact with a first portion of the second single crystal silicon layer; forming a capacitor in contact with a second portion of the second single crystal silicon layer; and forming a gate electrode layer facing a third portion.