Three-Electrode Integrated Capacitors With Shared Via Access
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Solution Overview
Problem
Current semiconductor device manufacturing techniques face challenges in reducing impedance in large arrays of capacitors and varying voltages across multiple regions within these capacitors, while also requiring significant real estate for power and ground vias.
Innovation Solution
The integration of capacitors with three electrodes each, directly accessing power and ground through a substrate, eliminates the need for separate ground and power vias, reduces impedance, and allows for varying voltages across multiple regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate ground vias and power vias are used to provide power and ground to capacitors, then reliable power and ground connections are achieved, but the real estate required increases and impedance increases
Solution Approach 1:
The patent merges the ground via and power via into a single shared via structure. Multiple capacitors share common ground and power connections through consolidated via paths, eliminating the need for separate dedicated vias for each capacitor. This merging reduces the total area occupied by via structures while maintaining reliable electrical connections for power and ground distribution across the capacitor array.
2Reliability
If separate ground vias and power vias are used, then distinct power and ground paths are provided, but impedance increases due to longer travel distance
Solution Approach 1:
The patent consolidates power and ground via paths into shared structures that reduce the overall current travel distance. By merging separate via paths into consolidated connection points, the effective impedance is reduced while still providing distinct electrical separation between power and ground functions through the capacitor structure design.
3Reliability
If traditional capacitor arrays are used with separate power and ground vias, then each capacitor has dedicated connections, but the overall array size becomes large
Solution Approach 1:
The patent implements shared via structures where multiple capacitors connect to common power and ground nodes. This merging approach allows capacitors to share connection infrastructure rather than each having dedicated vias, significantly reducing the overall array footprint while maintaining reliable electrical connections for all capacitor elements.
Solution Approach 2:
The shared via structures serve multiple functions simultaneously - providing power connections to multiple capacitors, providing ground connections to multiple capacitors, and acting as common distribution nodes. This multi-functionality allows a single via structure to replace what would traditionally require multiple separate via structures, reducing the overall array size.
4Quantity of substance
If massive capacitor arrays are formed, then capacitance for multiple IC devices is provided, but impedance increases without proper via configuration
Solution Approach 1:
The patent merges via paths to create consolidated power and ground distribution networks that serve the entire capacitor array. This merging reduces the total number of via structures needed and creates lower-impedance paths for current flow across the massive capacitor array, enabling high capacitance capacity without proportionally high impedance.
Data Source
AI summary
A component comprises a substrate comprising a first side and a second side opposite to the first side. A first dielectric layer is formed on the first side, and a plurality of electrically conductive pads extend through the first dielectric layer. A second dielectric layer is formed on the second side, and a plurality of electrically conductive pads extend through the second dielectric layer. A plurality of capacitors are each formed in an opening that extends at least partially from the first side towards the second side of the substrate. Each of the capacitors comprises at least three electrodes. At least one of the plurality of capacitors is coupled on the first side to an electrically conductive pad of the first dielectric layer and is coupled on the second side to an electrically conductive pad of the second dielectric layer.