Three-Gate Flash Memory Cell Fabrication via Dual Polysilicon Deposition
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Solution Overview
Problem
As non-volatile flash memory cells shrink in size, it becomes increasingly challenging to fabricate self-aligned elements with reduced processing steps, such as masking and polysilicon deposition steps, complicating the fabrication process.
Innovation Solution
A simplified method for forming non-volatile memory cells involves forming insulation blocks and spacers on a semiconductor substrate, followed by polysilicon deposition and etching processes to create source and drain regions, reducing the number of polysilicon deposition steps while maintaining the integrity of the floating, erase, and word line gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of polysilicon deposition steps is reduced to two, then the fabrication process is simplified and productivity is improved, but the difficulty of forming self-aligned elements increases
Solution Approach 1:
The patent segments the polysilicon deposition into two distinct steps: first forming the floating gate and erase gate in one deposition, then forming the word line gate in a second deposition. This segmentation allows each polysilicon layer to serve specific functions with appropriate thickness and doping characteristics, simplifying the overall process while maintaining self-alignment through the sequential nature of the depositions.
Solution Approach 2:
The patent uses preliminary patterning and insulation block formation before the first polysilicon deposition to pre-establish the geometric framework for self-alignment. The insulation blocks and spacers are formed in advance to define where the polysilicon will be deposited and retained, ensuring proper alignment without requiring complex simultaneous patterning steps.
2Area of moving object
If memory cell size is reduced, then device density is improved, but the difficulty of fabricating self-aligned elements increases
Solution Approach 1:
The patent applies local quality by forming insulation blocks with specific dielectric properties in critical areas to maintain precise spacing and alignment as device dimensions shrink. The varying thicknesses of polysilicon layers (thinner floating gate, thicker word line gate) are locally optimized to maintain electrical performance and self-alignment in miniaturized devices.
Solution Approach 2:
The patent uses vertical dimensionality through multi-layer polysilicon deposition and insulation block structures to maintain horizontal spacing and alignment. By utilizing the vertical stacking of insulation blocks, spacers, and polysilicon layers, the design achieves precise self-alignment in the horizontal plane even as device footprints are reduced.
3Device complexity
If the number of masking steps is reduced, then the fabrication process is simplified, but the precision of element formation may be compromised
Solution Approach 1:
The patent employs self-aligned processes where previously formed structures serve as their own masks. The insulation blocks and spacers automatically define the boundaries for polysilicon deposition without requiring additional photolithography masking steps, maintaining precision through geometric self-constraint rather than optical masking.
Solution Approach 2:
The patent merges multiple functions into the insulation block and spacer structures: they serve as physical masks for polysilicon deposition, define etch boundaries, provide electrical isolation, and establish mechanical support. This consolidation eliminates the need for separate masking steps while maintaining formation precision through the integrated nature of these multi-functional elements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the fabrication process by reducing the number of polysilicon deposition steps to two, enabling efficient formation of memory cells with improved erase efficiency and reliable gate structures, specifically a sharp-tipped floating gate and thick nitride block acting as a hard mask.
Implementation Method 1
forming a first polysilicon layer on the first insulation layer in a first polysilicon deposition process
Implementation Method 2
forming a second polysilicon layer over the substrate and the pair of insulation blocks in a second polysilicon deposition process
Data Source
AI summary
A simplified method for forming a non-volatile memory cell using two polysilicon depositions. A first polysilicon layer is formed on and insulated from the semiconductor substrate in a first polysilicon deposition process. An insulation block is formed on the first polysilicon layer. Spacers are formed adjacent first and second sides of the insulation block, and with the spacer adjacent the first side is reduced. Exposed portions of the first poly silicon layer are removed while maintaining a polysilicon block of the first polysilicon layer disposed under the insulation block. A second polysilicon layer is formed over the substrate and the insulation block in a second polysilicon deposition process. Portions of the second polysilicon layer are removed while maintaining a first polysilicon block (disposed adjacent the first side of the insulation block), and a second polysilicon block (disposed adjacent the second side of the insulation block).