Three-Junction LED Layout for Low-Voltage Synchronous Driving
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Solution Overview
Problem
Existing polychromatic LED devices face challenges in synchronous low-voltage driving due to the need for multiple contact terminals, which complicates fabrication and increases device footprint, and are not compatible with common anode or cathode display driving methods.
Innovation Solution
A three-junction LED design with sequential p-n junctions, including an n/p tunnel junction and a p/n tunnel junction, and a current blocking layer, allows for five-terminal configuration that supports synchronous driving with a common terminal, reducing contact terminals and facilitating smaller pixel pitch or larger light-emitting area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If six isolated contacts are used to avoid synchronous driving problems, then synchronous driving compatibility is improved, but device fabrication difficulty increases and device footprint becomes larger
Solution Approach 1:
The patent combines multiple contact functions into fewer contacts by using a common n-type contact layer that serves multiple p-n junctions simultaneously. This merging approach reduces the number of contacts from six to five while maintaining synchronous driving capability, as the common contact can be driven at a fixed potential while other contacts are modulated for synchronous operation.
Solution Approach 2:
The common n-type contact layer performs multiple functions: it serves as the cathode for multiple p-n junctions, provides a reference potential for synchronous driving, and enables current injection into multiple junctions simultaneously. This multi-functionality reduces the overall contact count while preserving driving compatibility.
2Adaptability or versatility
If six isolated contacts are used to avoid synchronous driving problems, then synchronous driving compatibility is improved, but device footprint becomes larger
Solution Approach 1:
By merging the contact functions and using a shared n-type contact layer, the patent reduces the number of contact vias required from six to five. This directly reduces the device footprint area while maintaining the ability to drive multiple junctions synchronously at low voltage.
3Adaptability or versatility
If four terminal devices with different stacking orders are used, then synchronous driving compatibility is improved, but manufacturing precision requirements increase due to complex epitaxial stacking
Solution Approach 1:
The patent applies local quality by using different stacking orders only where necessary - specifically, one p-n junction uses n-type layer grown first while another uses p-type layer grown first. This localized variation in stacking order enables synchronous driving compatibility without requiring complex different stacking sequences throughout the entire device, thus reducing manufacturing precision requirements compared to four-terminal designs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enables efficient synchronous driving of multiple junctions at low voltage, minimizing diffusion of dopants and point defects, and enhances internal quantum efficiency, facilitating easier wafer fabrication and smaller pixel pitches.
Implementation Method 1
an n/p tunnel junction; a p/n tunnel junction
Implementation Method 2
A light emitting diode (LED) is a semiconductor light source that emits visible light when current flows through it
Implementation Method 3
a current blocking layer disposed between two of the n-type layers
Data Source
AI summary
Provided is a three p-n junction polychromatic LED compatible with synchronous driving of multiple junctions at low applied voltage. Semiconductor contact layers are isolated from each other by inserting epitaxial current blocking layers between them. Two of the p-n junctions are connected in parallel to the cathode (or anode) using the same n-type layer which allows for a configuration with only five terminals. The reduced number of contact terminals facilitates wafer fab processing and allows for a smaller pixel pitch or larger light-emitting area at a given pitch.