Three-Layer Floating Gate for Flash Memory Noise Reduction
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Solution Overview
Problem
As memory cells in non-volatile semiconductor storage systems, such as flash memory, are scaled down, they experience increased program noise due to quantum mechanical fluctuations and manufacturing variations, leading to deviations in threshold voltage changes during programming, resulting in over-programming and read errors.
Innovation Solution
Implementing a three-layer floating gate structure with specific dielectric layers and doping profiles, where the floating gate is composed of three polysilicon layers separated by dielectric layers, helps in reducing program noise by ensuring consistent threshold voltage changes and tighter threshold voltage distributions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are scaled down to increase storage capacity, then storage density is improved, but program noise increases due to quantum mechanical fluctuations and manufacturing variations
Solution Approach 1:
The floating gate is divided into three separate polysilicon layers (first, second, and third layers) instead of a single layer. This segmentation allows each layer to contribute to charge storage independently, reducing the impact of quantum mechanical fluctuations and manufacturing variations on any single layer, thereby decreasing program noise while maintaining high storage density.
Solution Approach 2:
Different regions of the floating gate structure are doped with different concentrations of dopants. The first polysilicon layer has a first dopant concentration, the second layer has a second dopant concentration, and the third layer has a third dopant concentration. This local quality variation optimizes charge storage characteristics in different regions, improving reliability by compensating for manufacturing variations.
2Quantity of substance
If memory cells are scaled down, then storage capacity increases, but threshold voltage control precision deteriorates due to increased program noise
Solution Approach 1:
Dividing the floating gate into three layers with different dopant concentrations enables more precise control over the overall threshold voltage. Each layer can be independently optimized to contribute a specific amount to the threshold voltage, allowing for finer control precision even as cell size decreases and storage capacity increases.
Solution Approach 2:
By varying the dopant concentration in each of the three polysilicon layers, the threshold voltage can be precisely controlled. The first layer has a first dopant concentration, the second layer has a second dopant concentration, and the third layer has a third dopant concentration, allowing for continuous adjustment of the overall threshold voltage characteristic to achieve desired precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The three-layer floating gate structure reduces program noise, leading to less over-programming and improved data integrity by maintaining uniform threshold voltage changes during programming and erasing, thus enhancing the reliability and endurance of memory cells.
Implementation Method 1
As memory cells in non-volatile semiconductor storage systems, such as flash memory, are scaled down, they experience increased program noise due to quantum mechanical fluctuations
Implementation Method 2
The threshold voltage Vt of the transistor is controlled by the amount of charge that is retained on the floating gate
Implementation Method 3
a first polysilicon layer, a first dielectric layer, a second polysilicon layer, a second dielectric layer, and a third polysilicon layer
Data Source
AI summary
A non-volatile storage system includes memory cells with floating gates that comprises three layers separated by two dielectric layers (an upper dielectric layer and lower dielectric layer). The dielectric layers may be an oxide layers, nitride layers, combinations of oxide and nitride, or some other suitable dielectric material. The lower dielectric layer is close to the bottom of the floating gate (near interface between floating gate and tunnel dielectric), while the upper dielectric layer is close to top of the floating gate (near interface between floating gate and inter-gate dielectric).