Three-Layer Gate Contact Structure for FinFET Resistance Reduction
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Solution Overview
Problem
The increasing demand for high-performance semiconductor devices with fine patterns and three-dimensional channel structures poses challenges in achieving improved electrical characteristics due to limitations in planar metal oxide semiconductor FETs, necessitating the development of advanced semiconductor devices like FinFETs.
Innovation Solution
The semiconductor device incorporates a gate contact structure with multiple layers, including a conductive first layer, a second layer with first impurities, and a third layer with different impurities, designed to enhance electrical conductivity and reduce resistance by using specific materials and deposition processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a simple gate contact structure is used, then device complexity is reduced, but electrical conductivity and resistance characteristics deteriorate
Solution Approach 1:
The gate contact structure is divided into three distinct layers: a first layer (e.g., tungsten) providing low resistance, a second layer (e.g., silicon-containing layer) improving adhesion and reducing stress, and a third layer (e.g., titanium nitride) enhancing barrier properties. This segmentation allows each layer to contribute specific properties that collectively improve electrical conductivity while maintaining structural integrity.
Solution Approach 2:
The gate contact structure employs composite material architecture combining different materials with complementary properties. The first layer uses a highly conductive material like tungsten, the second layer incorporates silicon-containing material for stress management, and the third layer uses titanium nitride for barrier functionality. This composite approach optimizes electrical conductivity while managing mechanical stresses in high aspect ratio structures.
2Productivity
If planar metal oxide semiconductor FETs are used, then manufacturing is simpler, but operating characteristics and performance are limited
Solution Approach 1:
The invention transitions from planar two-dimensional channel structures to three-dimensional FinFET channel structures with vertical fins. This dimensional change increases the effective channel width and surface area for carrier transport, significantly improving device performance and driving current while maintaining scalability for high integration.
Solution Approach 2:
The FinFET structure changes key geometric parameters including channel width, channel length, and vertical fin height. By optimizing these parameters, the device achieves improved operating characteristics, higher drive current, and better control over channel conductivity compared to planar structures, directly enhancing productivity and performance.
3Area of stationary object
If gate contact structure layers are placed close to interlayer insulating layer, then area is reduced, but stress control and adhesion deteriorate
Solution Approach 1:
The second layer is strategically positioned between the first layer and the interlayer insulating layer, creating a localized stress management zone. This layer has specific material properties (silicon-containing) that provide both adhesion to the conductive first layer and stress relief against the interlayer insulating layer, maintaining strong bonds while controlling mechanical stress in this critical local region.
Solution Approach 2:
The second layer acts as an intermediary between the first conductive layer and the interlayer insulating layer. It provides adhesion promotion while managing stress transmission, preventing direct contact between the conductive material and insulating layer, thereby maintaining both area efficiency and mechanical strength through this mediating layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The layered gate contact structure effectively reduces resistance and improves electrical characteristics of the semiconductor device, particularly in high aspect ratio structures, ensuring reliable performance and efficiency.
Implementation Method 1
a first layer including a conductive material... connected to the gate electrode
Implementation Method 2
a second layer provided on the first layer and including first impurities
Implementation Method 3
a third layer provided on the second layer and including second impurities that are different from the first impurities
Data Source
AI summary
A semiconductor device includes a substrate; an active region extending in a first direction on the substrate; a gate structure extending in a second direction on the substrate and including a gate electrode; a source/drain region provided on the active region on at least one side of the gate structure; an interlayer insulating layer covering the gate structure; a first contact structure connected to the source/drain region on at least one side of the gate structure; and a gate contact structure passing at least partially through the interlayer insulating layer and connected to the gate electrode, wherein the gate contact structure includes: a first layer including a conductive material; a second layer provided on the first layer, spaced apart from the interlayer insulating layer by the first layer, and including first impurities; and a third layer provided on the second layer and including second impurities.