Three-Level Inverter Current Limiting Control Method
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Solution Overview
Problem
Existing current limiting techniques for three-level inverters suffer from poor output voltage waveforms and excessive switching losses due to increased switching frequency of switch transistors, particularly in wave-by-wave current limiting methods, which can lead to overvoltage risks and energy irrigation between buses.
Innovation Solution
Implementing a current limiting control method where auxiliary switch transistors are directly turned on when the current output drops below the threshold, and main switch transistors are turned on at the next PWM effective edge, thereby reducing switching frequency and loss by limiting the number of current limit switchings within each cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If wave-by-wave current limiting is adopted for auxiliary switch transistors, then output voltage waveform quality is improved, but switching frequency increases excessively causing high switching losses
Solution Approach 1:
The patent applies periodic action by synchronizing auxiliary switch transistor turn-on with PWM effective edges, ensuring current limiting occurs only at appropriate periodic intervals rather than continuously. This reduces unnecessary switching events while maintaining waveform quality during actual current limit conditions.
Solution Approach 2:
The patent uses preliminary action by predicting current limit conditions based on output voltage waveform characteristics and proactively preparing the de-blocking logic timing. This allows the system to anticipate when current limiting will occur and pre-position the auxiliary switches to turn on at the next PWM effective edge, avoiding excessive reactive switching.
2Loss of energy
If non-wave-by-wave current limiting is adopted, then switching losses are reduced, but overvoltage risk to unilateral bus increases
Solution Approach 1:
The patent implements feedback by continuously monitoring output voltage waveform characteristics and using this information to determine the appropriate timing for auxiliary switch transistor turn-on. The de-blocking logic timing is adjusted based on real-time waveform analysis, ensuring current limiting occurs at optimal moments that prevent overvoltage while minimizing switching events.
Solution Approach 2:
The patent applies dynamics by making the current limiting strategy adaptive rather than fixed. The system dynamically selects between wave-by-wave and non-wave-by-wave approaches based on real-time operating conditions, adjusting the de-blocking logic timing to match the actual current and voltage states, thus optimizing both waveform quality and switching loss reduction.
3Speed
If auxiliary switch transistors are turned on immediately when current limit signal disappears, then response speed is improved, but switching frequency multiplies excessively
Solution Approach 1:
The patent applies periodic action by aligning auxiliary switch transistor turn-on with PWM effective edges, which occur at regular periodic intervals. This ensures the system responds quickly to current limit conditions while constraining switching events to occur only at these predetermined periodic moments, preventing excessive switching frequency multiplication.
Data Source
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AI summary
A current limiting control method for a three-level inverter, comprising the following steps: S1. when a current output from a bridge arm is greater than or equal to a current limiting threshold and a received overcurrent signal is enabled, first turning off the main switch transistors and then turning off the auxiliary switch transistors; S2. when the current output from the bridge arm drops to lower than the current limiting threshold and the received overcurrent signal is disabled, turning on the auxiliary switch transistors; S3. when the received overcurrent signal is disabled and a next PWM effective edge of the main switch transistors arrives, turning on the main switch transistors. The present invention relates also to a current limiting control device for a three-level inverter. By implementing the present invention, when the current output from the bridge arm drops to lower than the current limiting threshold, the auxiliary switch transistors are directly turned on, making it possible to ensure voltage waveform quality, and when a next PWM effective edge of the main switch transistors arrives, the main switch transistors are turned on, making it possible to ensure that a switching frequency of the switch transistors will not excessively increase, so as to reduce switching loss.