Three-Level Inverter Semiconductor Module Vertical Current Paths
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Power semiconductor modules with three-level inverter circuits face challenges in reducing wiring inductance while maintaining or increasing current-carrying capacity, leading to larger module sizes and increased inductance difficulties.
Innovation Solution
A semiconductor device configuration with multiple semiconductor units connected in parallel, utilizing a multi-layer substrate and printed circuit boards with conductive posts to reduce wiring inductance, allowing for a more compact design and higher current capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the surface area of the multi-layer substrate is increased to allow for a larger amount of current, then the current-carrying capacity is improved, but the size of the power semiconductor module increases and the inductance of the wiring becomes more difficult to restrain
Solution Approach 1:
The patent transitions from planar current paths to three-dimensional vertical current paths by stacking multiple semiconductor chips and substrates. The connection terminals extend vertically through the module structure, allowing current to flow in the thickness direction rather than only in the plane, thereby increasing current capacity without expanding the module's footprint area.
Solution Approach 2:
The patent implements a nested structure where semiconductor chips are mounted on substrates, which are then stacked and connected through connection terminals that pass through multiple layers. The connection terminals are embedded within the substrate structure, creating a compact nested arrangement that maximizes current capacity within a confined volume.
2Quantity of substance
If the surface area of the multi-layer substrate is increased to allow for a larger amount of current, then the current-carrying capacity is improved, but the inductance of the wiring becomes more difficult to restrain
Solution Approach 1:
The patent reduces wiring inductance by changing the current path from horizontal to vertical. The connection terminals extend perpendicular to the substrate planes, creating short current loops that minimize the area enclosed by current paths. This vertical arrangement significantly reduces inductance compared to traditional planar wiring while accommodating high current loads.
Solution Approach 2:
The patent divides the current path into multiple segmented sections through the stacked substrate structure. Each substrate layer has its own connection terminals that are electrically connected, creating multiple parallel current paths. This segmentation allows current to be distributed across multiple short vertical segments rather than one long horizontal path, reducing overall inductance.
3Quantity of substance
If multiple semiconductor units are connected in parallel to increase current capacity, then the current-carrying capacity is improved, but the device complexity increases
Solution Approach 1:
The patent merges multiple semiconductor units into a single integrated module structure. Multiple substrates are stacked and bonded together, with connection terminals that electrically connect corresponding pads across all layers. This combining approach achieves parallel current capacity equivalent to multiple separate units while presenting a single compact device with simplified external connections.
Solution Approach 2:
The connection terminals serve multiple functions simultaneously: they provide electrical connection between stacked substrates, act as current carriers for high current capacity, and serve as external connection points for the module. This multi-functionality reduces the need for separate components and simplifies the overall device structure while maintaining high current capability.
Data Source
AI summary
A semiconductor device including: a plurality of semiconductor units each constituting a three-level inverter circuit; and a connection unit electrically connecting the plurality of semiconductor units in parallel, wherein each of the semiconductor units includes: a multi-layer substrate including an insulating plate and circuit plates disposed on a primary surface of the insulating plate; a plurality of semiconductor elements each having a back surface thereof fixed to one of the circuit plates and a front surface thereof having primary electrodes; and wiring members electrically connected to the primary electrodes of the semiconductor elements, and wherein in each of the semiconductor units, the multi-layer substrate, the plurality of semiconductor elements, and the wiring members are configured in such a way as to constitute the three-level inverter circuit.