Three-Level Inverter PWM Control for Common-Mode and Harmonic Suppression
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Solution Overview
Problem
Existing common-mode voltage suppression methods for coupled three-level inverters are inadequate when operating under unbalanced capacitor voltages on the direct current side, leading to increased output current harmonics and limited output states, and cannot generate medium vectors effectively.
Innovation Solution
A method and system for cooperatively suppressing common-mode voltage and current harmonics by determining the sector and region of the reference voltage vector, selecting basic voltage vectors with low amplitudes, calculating duty cycles through a volt-second balance equation, and designing a switching sequence to control the inverter, even in conditions of unbalanced capacitor voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If existing common-mode voltage suppression method is used, then common-mode voltage is suppressed under balanced capacitor voltage conditions, but output current harmonics increase and medium vectors cannot be generated under unbalanced capacitor voltage conditions
Solution Approach 1:
The patent implements dynamic switching sequence selection based on the balance state of capacitor voltages. The control method dynamically adjusts the switching sequence according to whether the capacitor voltages are balanced or unbalanced, enabling the system to adapt to different operating conditions. This dynamic adaptation allows the generation of medium vectors under unbalanced conditions while maintaining common-mode voltage suppression, resolving the contradiction between suppressing harmful common-mode voltage and maintaining adaptability to varying capacitor voltage conditions.
2Power
If conventional space vector modulation method is used, then voltage control is achieved, but common-mode voltage suppression and separate capacitor voltage control cannot be realized simultaneously under unbalanced conditions
Solution Approach 1:
The patent segments the control process into distinct phases: determining capacitor voltage balance state, selecting appropriate switching sequences, calculating duty cycles through volt-second balance equations, and generating PWM signals. This segmentation allows the complex control task to be divided into manageable steps, enabling simultaneous achievement of voltage control, common-mode voltage suppression, and separate capacitor voltage control without overwhelming system complexity.
Solution Approach 2:
The patent changes key control parameters including switching sequences, duty cycles, and voltage difference references based on the capacitor voltage balance state. By dynamically adjusting these parameters, the system achieves effective common-mode voltage suppression and separate capacitor voltage control while maintaining proper voltage control capability, resolving the contradiction between power control and device complexity.
3Object-affected harmful factors
If basic voltage vectors with low common-mode voltage amplitudes are selected, then common-mode voltage is suppressed, but the ability to generate medium vectors is limited under unbalanced conditions
Solution Approach 1:
The patent employs feedback mechanisms by continuously monitoring capacitor voltage balance state and using this information to adjust switching sequences and duty cycles. The volt-second balance equations incorporate feedback from actual capacitor voltages to maintain proper voltage control. This feedback ensures that medium vectors can be generated when needed while maintaining low common-mode voltage amplitudes, resolving the contradiction between suppressing harmful factors and ensuring output waveform quality.
Data Source
AI summary
The present invention provides a method for cooperatively suppressing a common-mode voltage and current harmonics of coupled three-level inverters, comprising: based on amplitude and phase angle of reference voltage vector, determining sector and region in which the reference voltage vector is located; selecting four basic voltage vectors with low common-mode voltage amplitudes to synthesize the reference voltage vector; writing volt-second balance equation based on selected basic voltage vectors, and calculating duty cycles thereof; and based on sector and region in which reference voltage vector is located, set value of voltage difference across capacitors on direct current side, and actual value of voltage difference across capacitors on direct current side, (1) updating duty cycles of basic voltage vectors, to realize separate control of capacitor voltage; and (2) designing and converting switching sequence into PWM drive signal of power switch, to control the coupled three-level inverter to operate.