Three-Level Output Driver Circuit for LPDDR Throughput and Power
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Solution Overview
Problem
Existing output drivers for LPDDR DRAM systems are complex and consume high power, especially when implementing multi-level communication to achieve improved throughput.
Innovation Solution
The implementation of an output driver with a high logic level driver, a low logic level driver, and an intermediate logic level driver, each coupled to a data terminal and controlled by specific voltage levels (VDDQ1, VDDQ2, and VSS) and control signals, to provide output data signals with three logic levels without significantly increasing circuit complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-level communication is implemented to improve throughput, then data transmission capacity increases, but output driver circuit complexity increases
Solution Approach 1:
The output driver is segmented into multiple independent drivers (first output driver, second output driver, third output driver) each handling specific logic levels. This segmentation allows each driver to be optimized independently for its specific function, reducing overall circuit complexity while enabling multi-level communication capability.
Solution Approach 2:
Each output driver is designed to provide multiple logic levels (first logic level, second logic level, third logic level) through universal control signals. This multi-functionality allows a single driver structure to handle various voltage levels without requiring separate dedicated circuits for each level, thereby reducing complexity.
2Productivity
If multi-level communication is implemented to improve throughput, then data transmission capacity increases, but power consumption increases
Solution Approach 1:
The output drivers are dynamically controlled through control signals that selectively activate only the necessary drivers for the current data transmission requirement. This dynamic control allows the system to consume power only when needed and at the minimal level required for the specific logic level being transmitted, reducing overall power consumption while maintaining high throughput capability.
Solution Approach 2:
Each output driver is optimized with specific voltage levels (first voltage level, second voltage level, third voltage level) tailored to its function. This local optimization ensures that power is efficiently utilized at each driver stage, minimizing wasted energy while achieving the required throughput through multi-level communication.
3Productivity
If output drivers are added to provide intermediate logic levels, then current consumption should increase, but the patent aims to reduce current consumption
Solution Approach 1:
A termination circuit is introduced as an intermediary element coupled to the data terminal, providing a controlled impedance path that reduces the current burden on the intermediate logic level driver. This intermediary structure allows the third output driver (providing intermediate logic levels) to operate with reduced current consumption while still achieving the required signal levels at the data terminal.
Data Source
AI summary
Apparatuses including output drivers and methods for providing output data signals are described. An example apparatus includes a high logic level driver, a low logic level driver, and an intermediate logic level driver. The high logic level driver is provided a first voltage and provides a high logic level voltage to a data terminal when activated. The low logic level driver is provided a second voltage and provides a low logic level voltage to the data terminal when activated. The intermediate logic level driver is provided a third voltage having a magnitude that is between the first and second voltages, and provides an intermediate logic level voltage to the data terminal when activated. Each of the high, low, and intermediate logic level drivers are configured to be respectively activated based on one or more of a plurality of control signals.