Three-Node Access Device Gate Dielectric Replacement for 3D Memory
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Solution Overview
Problem
As design rules shrink, semiconductor space for fabricating memory devices like DRAM arrays becomes limited, leading to challenges in forming efficient access devices with reduced off-current and gate/drain induced leakage.
Innovation Solution
The formation of three-node horizontal access devices without body region contacts, integrated with vertical access lines and horizontal digit lines, using gate dielectric material replacement fabrication steps, and avoiding gas phase doping, which allows for better lateral scaling and reduced leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If design rules are shrunk to increase memory density, then semiconductor space utilization is improved, but off-current and gate/drain induced leakage increase
Solution Approach 1:
The patent transitions from planar 2D memory architecture to vertical 3D architecture by stacking multiple memory layers along the vertical dimension. This dimensional change allows increased memory density without further shrinking lateral design rules, thereby maintaining acceptable leakage characteristics while achieving higher storage capacity through vertical stacking of memory cells and access devices.
Solution Approach 2:
The patent implements selective doping regions with different doping types and concentrations in specific locations within the access device structure. By creating locally optimized regions with tailored electrical properties, the invention reduces off-current and gate/drain induced leakage at critical interfaces while maintaining overall device functionality and scaling compatibility.
2Ease of manufacture
If access devices are formed with traditional structures, then manufacturing process is simpler, but lateral scaling capability is limited
Solution Approach 1:
The patent divides the access device into segmented regions including source regions, drain regions, channel regions, and selectively doped body regions. This segmentation allows each region to be independently optimized and formed through separate fabrication steps, enabling better lateral scaling while maintaining manufacturing feasibility through modular device architecture.
Solution Approach 2:
The invention moves from lateral scaling in 2D to vertical stacking in 3D, allowing continued scaling of memory density by adding vertical layers rather than shrinking lateral dimensions. This dimensional transition preserves manufacturing process simplicity while achieving superior scaling through vertical integration of multiple memory cell layers.
3Reliability
If body region contacts are included in access devices, then device control is improved, but device complexity and fabrication difficulty increase
Solution Approach 1:
The patent extracts or removes the body region contact from the traditional access device structure. By eliminating this additional contact requirement, the invention simplifies the device architecture and fabrication process while maintaining sufficient control over the channel region through alternative doping and gating mechanisms implemented in the vertical 3D structure.
Solution Approach 2:
The patent integrates multiple functions into the gate structure and doping regions, where the gate simultaneously provides channel control and the selectively doped regions provide body effect modulation without requiring separate body contacts. This functional integration reduces device complexity while maintaining reliable electrical control.
Data Source
AI summary
Systems, methods, and apparatus are provided for storage node after horizontally oriented, three-node access device formation in vertical three dimensional (3D) memory. An example method includes a method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and vertically oriented access lines. The method includes depositing alternating layers of a dielectric material and a sacrificial semiconductor material to form a vertical stack. A first vertical opening is formed through the vertical stack to expose a first region of the sacrificial semiconductor material. The first region is selectively removed to form a first horizontal opening in which to replace a sacrificial gate dielectric material, form a source/drain conductive contact material, a channel conductive material, and a digit line conductive contact material of the three-node access device.