Three-Part Source/Drain Structure for Transistor Underfill
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Solution Overview
Problem
Advanced transistor fabrication faces challenges in forming source/drain regions between adjacent gate structures with different gate pitches, leading to issues such as underfill, increased short-channel effects, higher contact resistance, and poor effective capacitance.
Innovation Solution
A three-part source/drain region structure is created, comprising a pair of spaced semiconductor spacers, a first semiconductor layer with a higher dopant concentration laterally between the spacers, and a second semiconductor layer with a lower dopant concentration over the first layer, all epitaxially grown, to address the underfill issue and enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If source/drain regions are formed between adjacent gate structures with different gate pitches, then transistor fabrication can proceed, but underfill occurs leading to insufficient volume and non-planar surfaces
Solution Approach 1:
The source/drain region is divided into three distinct parts with different dopant concentrations: a first doped region, a second doped region with higher concentration, and a third doped region with lower concentration. This segmentation allows each region to be optimized independently for volume, planarity, and electrical performance, resolving the underfill and non-planar surface issues while maintaining fabrication feasibility
Solution Approach 2:
Different regions of the source/drain structure are assigned different dopant concentrations tailored to their specific functional requirements. The second doped region has higher concentration to reduce contact resistance, while the third doped region has lower concentration to improve effective capacitance. This local quality differentiation enables simultaneous achievement of volume, planarity, and electrical performance
2Ease of operation
If source/drain regions are formed with larger lateral space between longer gate structures, then fabrication is easier, but underfill issues occur leading to performance degradation
Solution Approach 1:
The source/drain region is segmented into three parts with progressively different dopant concentrations. The first doped region provides structural foundation, the second doped region with higher concentration ensures low contact resistance, and the third doped region with lower concentration maintains effective capacitance. This segmentation allows the structure to achieve both fabrication ease and reliable performance despite larger lateral spacing
Solution Approach 2:
The dopant concentration parameter is varied across different regions of the source/drain structure. By changing the dopant concentration from the first to second to third doped regions, the invention optimizes electrical properties (contact resistance and effective capacitance) while maintaining structural integrity and performance reliability across different gate pitch configurations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This structure improves short-channel effects, reduces contact resistance, and increases effective capacitance by providing a more uniform and voluminous source/drain region, effectively addressing the challenges of underfill and performance degradation.
Implementation Method 1
The different parts of the source/drain region may each have a different dopant concentration
Data Source
AI summary
A structure for a field-effect transistor includes a semiconductor body, a first gate structure extending over the semiconductor body, and a second gate structure extending over the semiconductor body. A recess is in the semiconductor body between the first and second gate structures. A three part source/drain region includes a pair of spaced semiconductor spacers in the recess; a first semiconductor layer laterally between the pair of semiconductor spacers; and a second semiconductor layer over the first semiconductor layer. The pair of spaced semiconductor spacers, the first semiconductor layer and the second semiconductor layer may all have different dopant concentrations.