Three-Phase Buck-Boost Converter Single PWM Control
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Solution Overview
Problem
Existing DC-DC converters face inefficiencies when operating in buck-boost mode, particularly in managing inductor current phases and requiring multiple pulse-width modulating signals, which increases silicon die area and quiescent current consumption.
Innovation Solution
A DC-DC converter operates in buck-boost mode using only one pulse-width modulating signal, with three distinct phases per clock pulse, allowing the inductor to charge, discharge, and maintain a constant non-zero value, and employing a PWM comparator and switch logic circuit to regulate output voltage efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple pulse-width modulating signals are used for buck-boost operation, then the converter can manage inductor current phases, but the silicon die area and quiescent current consumption increase
Solution Approach 1:
The patent combines multiple pulse-width modulating signals into a single pulse-width modulating signal for controlling the buck-boost converter. This single signal coordinates all switch elements (S1, S2, S3, S4) to achieve the desired inductor current phase management, thereby reducing the silicon die area required for generating and managing multiple separate control signals.
Solution Approach 2:
The single pulse-width modulating signal serves multiple functions simultaneously: it controls the timing of inductor current phases, coordinates switch operations, and manages both buck and boost modes of operation. This multi-functionality eliminates the need for separate control signals for each function, reducing overall system complexity and die area.
2Reliability
If multiple pulse-width modulating signals are used for buck-boost operation, then the converter can manage inductor current phases, but the quiescent current consumption increases
Solution Approach 1:
The patent merges multiple control signal generation functions into a single pulse-width modulating signal pathway, reducing the number of active control circuits required. This consolidation decreases the quiescent current consumption associated with maintaining multiple separate signal generation and management circuits.
Solution Approach 2:
The single pulse-width modulating signal performs multiple control functions including phase management, switch timing coordination, and mode transition control. By having one signal perform multiple functions, the patent reduces the total power consumption compared to having separate dedicated signals for each function.
3Power
If traditional buck-boost topology is used, then voltage conversion is achieved, but the peak-peak ripple to average current ratio is high and inductor size is large
Solution Approach 1:
The patent divides the inductor current waveform into three distinct phases within each switching cycle: upward ramp phase, downward ramp phase, and constant current phase. This segmentation of the current waveform allows for better utilization of the inductor, reducing the required inductance value and physical size while maintaining effective voltage conversion.
Solution Approach 2:
The patent implements a periodic three-phase operation pattern where the inductor current follows a structured sequence of charging, discharging, and holding phases. This periodic action optimizes the current ripple characteristics, reducing the peak-peak to average current ratio and enabling smaller inductor dimensions.
Data Source
AI summary
A buck-boost converter is provided. In buck-boost mode, the converter operates in at least three phases. In one phase, the inductor current ramps upward. In another phase, the inductor current ramps downward. In yet another phase, the inductor current remains at roughly the same non-zero value. Only one pulse-width modulating signal is used in the buck-boost operation. A PWM comparator compares the pulse-width modulating signal with the error signal and trips when the error signal exceeds the pulse-width modulating signal. One of the three phases occurs at the beginning of the clock pulse before the PWM comparator trips. Another of the phases occurs while the PWM comparator is tripped. Yet another of the phases occurs from the time that the PWM goes from tripped to untripped until the beginning of the next clock cycle.