Three-Plate Capacitive Isolation for High Voltage Domain Communication
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Solution Overview
Problem
Existing capacitive isolation methods face challenges in achieving sufficient breakdown voltage due to physical space constraints in integrated circuits, particularly in CMOS processes where the maximum dielectric thickness is limited, leading to insufficient voltage isolation between circuits operating in different domains.
Innovation Solution
The use of a capacitive structure with three plates arranged in a series configuration, where two plates are in an upper layer and one plate is in a lower layer, with dielectric layers providing equal breakdown voltages, allowing for increased overall breakdown voltage and effective capacitive isolation between voltage domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the dielectric layer thickness is increased to provide higher breakdown voltage, then the breakdown voltage is improved, but the physical space required increases which conflicts with area constraints in integrated circuits
Solution Approach 1:
The patent divides a single thick dielectric layer into multiple thinner dielectric layers stacked in series. Each layer provides a portion of the total breakdown voltage, allowing the system to achieve high breakdown voltage without requiring a single excessively thick dielectric layer that would consume excessive area. The segmentation of the dielectric structure enables voltage distribution across multiple interfaces while maintaining compact footprint.
Solution Approach 2:
The patent transitions from a single-plane capacitor layout to a three-dimensional stacked configuration. By arranging capacitor plates and dielectric layers in multiple vertical layers, the design utilizes the vertical dimension to achieve higher breakdown voltage without proportionally increasing the horizontal area occupied on the chip. This dimensional transition allows compact integration of high-voltage isolation structures.
2Ease of manufacture
If a parallel plate capacitor is implemented in conventional CMOS processes, then manufacturing is simplified, but the maximum dielectric thickness is limited to about 5-10 um which is insufficient for high voltage applications
Solution Approach 1:
The patent segments the required total dielectric thickness into multiple thinner dielectric layers that can each be formed using standard CMOS process capabilities. Instead of requiring a single 10-20 um thick dielectric layer that exceeds process limits, the structure uses several 1-2 um layers stacked in series, each manufacturable with conventional techniques while collectively providing the necessary breakdown voltage.
Solution Approach 2:
The patent employs composite dielectric structures combining multiple dielectric materials or layered configurations to achieve the required electrical properties. By stacking different dielectric layers with appropriate breakdown characteristics, the design achieves high overall breakdown voltage while maintaining compatibility with standard CMOS fabrication processes that can handle multiple thin dielectric deposits.
3Reliability
If capacitive coupling is used for galvanic isolation between voltage domains, then signal transmission is enabled, but large voltage differences between domains require high breakdown voltage capacitors that are difficult to implement due to space constraints
Solution Approach 1:
The patent segments the high-voltage isolation requirement into multiple lower-voltage dielectric interfaces. By stacking several thin dielectric layers in series, each interface handles a portion of the total voltage difference, enabling galvanic isolation across large voltage domains while keeping individual capacitor footprints small and suitable for integrated circuit implementation.
Solution Approach 2:
The patent resolves the area constraint by moving from lateral expansion to vertical stacking. The multi-layer capacitor structure achieves high breakdown voltage through vertical layering rather than horizontal scaling, allowing sufficient voltage isolation between domains without occupying excessive chip area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively doubles the breakdown voltage compared to traditional two-plate capacitors, enabling reliable capacitive isolation and communication between circuits in different voltage domains, even in applications with large voltage differences.
Implementation Method 1
circuits may be galvanically isolated using capacitive coupling on signal paths between the circuits
Implementation Method 2
The breakdown voltage of the parallel plate capacitor is dependent on the thickness of the dielectric layer
Data Source
AI summary
In one or more embodiments, circuitry is provided for isolation and communication of signals between circuits operating in different voltage domains using capacitive coupling. The capacitive coupling is provided by one or more capacitive structures having a breakdown voltage that is defined by way of the various components and their spacing. The capacitive structures each include three capacitive plates arranged to have two plates located in an upper layer and one plate located in a lower layer. A communication signal can be transmitted via the capacitive coupling created between the lower plate and each of the upper plates, respectively.