Three-Plate MIM Capacitor Structure for Higher Capacitance Density
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Solution Overview
Problem
As integrated circuits (ICs) are scaled down, traditional metal-insulator-metal (MIM) devices fail to provide the required capacitance per unit area, limiting their application in small pixel-sized ICs.
Innovation Solution
A MIM device with a three-metal plate configuration, featuring two capacitor insulator structures, where the first and third metal plates are electrically coupled together and the second metal plate is separately coupled, enhancing capacitance by combining the capacitance of two capacitors in parallel, thus increasing capacitance for a given layout area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional MIM device structure is used, then device simplicity is maintained, but capacitance per unit area becomes insufficient for scaled-down ICs
Solution Approach 1:
The MIM device is segmented into multiple capacitor insulator structures (first, second, and third capacitor insulator structures) stacked vertically between the metal plates. This segmentation allows each insulator layer to contribute independently to the total capacitance, thereby increasing capacitance per unit area without requiring lateral expansion that would increase device footprint.
Solution Approach 2:
The patent transitions from a planar (2D) capacitor configuration to a vertical (3D) stacked configuration. By stacking capacitor insulator structures in the vertical dimension between the metal plates, the device achieves higher capacitance per unit area by utilizing the third dimension (height) rather than relying solely on lateral area expansion.
2Area of moving object
If MIM device is scaled down for small pixel ICs, then IC size is reduced, but capacitance performance becomes inadequate
Solution Approach 1:
The patent compensates for the reduced lateral area by exploiting the vertical dimension. Multiple capacitor insulator structures are stacked vertically between the metal plates, allowing the device to achieve sufficient total capacitance within a smaller footprint by increasing the effective capacitance-generating volume in the vertical direction.
Solution Approach 2:
The capacitor insulator structures are nested vertically between the metal plates, with each insulator layer contained within the same lateral footprint. This nesting arrangement allows multiple capacitance-contributing layers to occupy the same horizontal space, effectively multiplying the capacitance density within the constrained pixel area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The MIM device achieves improved capacitance performance, enabling its use in ICs with small single or dual pixel sizes where traditional MIM devices are inadequate.
Implementation Method 1
A first capacitor insulator structure is disposed between the first metal plate and the second metal plate and electrically insulates the first metal plate from the second metal plate
Data Source
AI summary
Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes a first conductive layer having a lower sidewall extending downward from a lower surface of the first conductive layer to within a recess in a lower dielectric, a second conductive layer over the first conductive layer, and a third conductive layer over the second conductive layer. A dielectric structure separates the first, second, and third conductive layers from one another. The dielectric structure continuously extends for a first thickness along an upper surface of the first conductive layer and for a second thickness along an upper surface of the second conductive layer. The second thickness is approximately one-half the first thickness. A conductive structure contacts a side of the first conductive layer. The conductive structure contacts a side of the third conductive layer along an interface entirely above a top of the lower sidewall.