Three-Port SRAM Cell Layout for Lower RC Delay and Write Margin
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Solution Overview
Problem
In the development of semiconductor integrated circuits, particularly in SRAM cells, there is a challenge in achieving high density and high speed while maintaining low RC delay for both bit lines and word lines, especially in deep sub-micron technology where the complexity of processing and manufacturing increases with scaling down, requiring innovative cell structures to meet the demands of high-speed communication and image processing applications.
Innovation Solution
The proposed solution involves a three-port SRAM memory cell design with a write port circuit and two read port circuits, utilizing fin-like field effect transistors (FinFETs) and gate-all-around field effect transistors (GAA FETs), where the read bit lines are arranged in the lowest metallization layer to decrease capacitance and increase read port speed, and the write bit lines are in higher layers to achieve lower resistance and improve write margin, thereby optimizing cell structure for both density and speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If read bit lines are placed in the lowest metallization layer, then capacitance is reduced, but manufacturing complexity increases due to multi-layer interconnect requirements
Solution Approach 1:
The patent utilizes the third dimension (vertical stacking of metallization layers) to resolve the RC delay issue. By placing read bit lines in the lowest metallization layer and write bit lines in higher layers, the patent exploits spatial separation in the vertical dimension to reduce capacitive coupling between bit lines and word lines, thereby reducing RC delay without increasing in-plane device complexity
Solution Approach 2:
The patent segments the metallization structure into multiple layers with specific functions assigned to each layer. The lowest metallization layer is dedicated to read bit lines, while higher layers accommodate write bit lines and word lines. This segmentation allows optimized electrical characteristics for different signal types while managing overall interconnect complexity
2Speed
If write bit lines are placed in higher metallization layers, then resistance is minimized, but device complexity increases
Solution Approach 1:
The patent places write bit lines in higher metallization layers (above the lowest layer) to exploit the vertical dimension for resistance optimization. This positioning reduces the length of vias and contacts required to reach the active transistor regions, thereby minimizing resistance and improving write margin
Solution Approach 2:
The patent applies different metallization layer assignments to different functional regions: read bit lines in the lowest layer for low capacitance, and write bit lines in higher layers for low resistance. This local optimization of interconnect structure tailors the electrical characteristics to the specific requirements of each port type
3Productivity
If three-port SRAM cell structure is implemented, then bandwidth is increased, but cell area increases
Solution Approach 1:
The patent merges multiple port functions into a single compact cell structure. By sharing transistor components and utilizing three-dimensional interconnect routing, the patent achieves three-port functionality (one write port, two read ports) without simply tripling the area of a conventional cell. The shared active structures and combined signal routing enable high bandwidth while maintaining area efficiency
Solution Approach 2:
The patent employs a nested arrangement where read port circuits are integrated within the same cell footprint as the write port circuit. The multi-layer metallization structure allows read and write bit lines to be vertically stacked, creating a nested three-dimensional layout that packs multiple functional ports into a minimized two-dimensional cell area
Data Source
AI summary
Semiconductor devices are provided. A write port circuit is configured to perform a write function according to the write word line and the first and second write bit lines. The first read port circuit is configured to perform first read function according to the first read bit line and the first read word line. The second read port circuit is configured to perform second read function according to the second read bit line and the second read word line. The transistors of the first and second read port circuits share a first active structure extending in the first direction. The first read bit line and the second read bit line extend in the first direction in a first metallization layer, and the first write bit line and the second write bit line extend in the first direction in a second metallization layer over the first metallization layer.