Three-Transistor-Set Latch for Rail-to-Rail High-Speed Output
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Solution Overview
Problem
Conventional latches consume high power and require voltage level shifters to convert non-rail-to-rail clock signals to rail-to-rail output signals, which is inefficient, especially in high-frequency applications like frequency dividers in communication systems.
Innovation Solution
Design of high-speed low-power latches with three sets of transistors: a first set for mode selection, a second set for capturing and providing input signals during the tracking mode, and a third set for storing and providing output signals during the holding mode, eliminating the need for voltage level shifters by operating with rail-to-rail voltage swing and differential signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional latches are used with voltage level shifters to convert non-rail-to-rail clock signals to rail-to-rail output signals, then the output signal voltage swing is sufficient, but the power consumption is high and the device complexity increases
Solution Approach 1:
The patent removes the voltage level shifter component from the conventional latch system. By designing the latch to natively operate with non-rail-to-rail clock signals and directly produce rail-to-rail output signals, the unnecessary voltage level conversion stage is eliminated, reducing both power consumption and device complexity.
Solution Approach 2:
The latch circuit is designed to perform multiple functions: it accepts non-rail-to-rail clock signals, performs frequency division, and directly generates rail-to-rail output signals all within a single integrated circuit. This multi-functionality eliminates the need for separate voltage level shifter components.
2Speed
If voltage level shifters are added to convert non-rail-to-rail clock signals to rail-to-rail output signals, then the output signal quality is improved, but the circuit speed decreases due to additional conversion stages
Solution Approach 1:
The voltage level shifter is removed from the signal path. The latch circuit directly generates rail-to-rail output signals from non-rail-to-rail clock inputs without intermediate conversion stages, eliminating signal degradation and delay associated with voltage level shifting.
Solution Approach 2:
The latch circuit is pre-designed with internal transistor configurations that directly produce rail-to-rail output swings. The cross-coupled transistor pairs and current mirror arrangements are configured beforehand to ensure full voltage swing output without requiring external voltage level conversion.
3Power
If conventional latch designs are used, then the circuit structure is simple, but the power consumption is high due to continuous operation of all transistor sets
Solution Approach 1:
The latch employs periodic switching of transistor sets based on clock signal phases. During each clock cycle, only the necessary transistor sets are activated while others remain in high-impedance or off states. This periodic activation pattern reduces average power consumption while maintaining continuous operational capability.
Solution Approach 2:
The latch circuit dynamically transitions between different operational states by selectively enabling or disabling transistor sets based on the clock signal phase and data input conditions. This dynamic operation allows the circuit to adapt its power consumption to actual operational needs, improving overall efficiency.
Data Source
AI summary
A high-speed low-power latch includes three sets of transistors. A first set of transistors selects a tracking mode or a holding mode for the latch based on a clock signal having non-rail-to-rail or rail-to-rail voltage swing. A second set of transistors captures a data value based on an input signal and provides an output signal during the tracking mode. A third set of transistors stores the data value and provides the output signal during the holding mode. The input and output signals have rail-to-rail voltage swing. In another aspect, a signal generator includes at least one latch and a control circuit. The latch(es) receive a clock signal and generate an output signal. The control circuit senses a duty cycle of a feedback signal derived from the output signal and generates a control signal to adjust operation of the latch(es) to obtain 50% duty cycle for the feedback signal.