Three-Side Gate Memory Device Leakage Prevention
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Solution Overview
Problem
Memory devices face challenges in increasing capacity and reducing size while avoiding high-temperature annealing, which causes short-channel effects and current leakage in metal-oxide-semiconductor devices, and require complex processes to achieve both low and high threshold voltages, increasing manufacturing costs.
Innovation Solution
A memory device design that includes a substrate with distinct regions, a stack structure with a floating gate and gate dielectric layer, isolation structures, and a control gate configuration that exposes the substrate's side surface to form a first gate dielectric layer, allowing the first gate to control the channel layer on three sides and reduce threshold voltage, thereby preventing leakage current, while using a simplified manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-temperature annealing process is used during manufacturing, then memory device can be fabricated, but short-channel effect occurs on metal-oxide-semiconductor device causing current leakage
Solution Approach 1:
The patent transitions from conventional planar gate configuration to a three-dimensional gate structure where the gate wraps around the channel from three sides. This dimensional change increases the effective gate control area without increasing the planar footprint, enabling better electrostatic control that prevents short-channel effects and current leakage while maintaining device scalability
Solution Approach 2:
The gate structure is segmented into multiple portions that wrap around the channel at different locations. This segmentation allows each gate portion to independently control specific regions of the channel, providing enhanced control over carrier flow and preventing leakage currents through improved electrostatic management
2Reliability
If metal-oxide-semiconductor device with high threshold voltage is formed, then current leakage is prevented, but operating speed becomes relatively low
Solution Approach 1:
The three-dimensional gate structure provides dynamic control capability where the wrapped gate configuration allows for more effective modulation of the channel conductivity. The increased gate control area enables stronger electric field induction, allowing the device to switch faster while maintaining high threshold voltage characteristics that prevent leakage
3Adaptability or versatility
If complicated process is used to form metal-oxide-semiconductor device with both low and high threshold voltage, then both types of devices can be formed on chip, but manufacturing cost increases
Solution Approach 1:
The patent applies local quality by configuring the three-dimensional gate structure differently in different regions of the chip. By adjusting the gate wrap-around geometry, gate material composition, or gate thickness in specific local areas, devices with different threshold voltages can be created using the same fundamental manufacturing process, eliminating the need for separate complex processing steps
Data Source
AI summary
A memory device including a substrate, a stack structure, an isolation structure, an inter-gate dielectric layer, a control gate, a first insulation structure, a first gate dielectric layer, and a first gate. The stack structure is disposed on the substrate. The isolation structure is disposed in the substrate and disposed at two sides of the stack structure. The inter-gate dielectric layer covers the stack structure and the isolation structure. The control gate covers the inter-gate dielectric layer. The first insulation structure is disposed in the substrate, wherein a top surface of the first insulation structure is lower than a top surface of the substrate, so that a side surface of a portion of the substrate is exposed. The first gate dielectric layer is disposed on the top surface and the side surface of the substrate. The first gate covers the first gate dielectric layer.