3D NAND Select Gate Transistor with Three-Sided Channel
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Solution Overview
Problem
Existing three-dimensional vertical NAND strings have limitations such as providing only one bit per cell and requiring a complex, time-consuming process for active region formation, resulting in a conical shape that is difficult to achieve.
Innovation Solution
A select gate transistor design with a semiconductor channel adjacent to three sides of the select gate electrode, featuring a gate insulating layer and a metal select gate, which includes epitaxial silicon channels for improved performance and a monolithic three-dimensional array structure for higher memory density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional NAND string structure is used, then the manufacturing process is simpler, but the memory density and performance are limited
Solution Approach 1:
The patent transitions from planar 2D transistor structures to three-dimensional vertical NAND strings with channels extending in the vertical dimension. The select gate electrode wraps around the channel from multiple sides (bottom, first side, second side), creating a 3D configuration that increases memory density without proportionally increasing manufacturing complexity
Solution Approach 2:
The select gate electrode is positioned to surround the channel from multiple directions, with the gate insulating layer nested between the gate electrode and channel. This nested configuration allows the gate to control the channel from three sides while maintaining a compact structure
2Manufacturing precision
If repeated sidewall spacer formation and etching are used to create active regions, then the process is more precise, but the manufacturing time and complexity increase significantly
Solution Approach 1:
The patent forms the gate insulating layer and select gate electrode structure before completing the channel formation process. By preparing the gate structure in advance, the patent eliminates the need for repeated sidewall spacer formation and etching steps that would otherwise be required to create precisely shaped active regions
Solution Approach 2:
Instead of forming the channel first and then adding the gate structure through multiple iterative steps, the patent inverts the sequence by forming the select gate electrode and gate insulating layer first, then completing the channel formation. This reversal simplifies the overall manufacturing process
3Length of moving object
If the channel is located adjacent to only two sides of the select gate electrode, then the device structure is simpler, but the channel length and performance are reduced
Solution Approach 1:
The select gate electrode extends not only laterally but also vertically, surrounding the channel from the bottom, first side, and second side. This three-dimensional gate configuration increases the effective channel length and improves device performance without requiring a proportionally complex structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables a longer semiconductor channel with a higher quality gate insulating layer and lower resistance select gate, leading to enhanced performance and higher memory density in vertical NAND devices.
Implementation Method 1
a gate insulating layer located between the channel and the first side, the second side and the bottom of the select gate electrode
Implementation Method 2
which includes epitaxial silicon channels for improved performance
Data Source
AI summary
A select gate transistor for a NAND device includes a select gate electrode having a first side, a second side, and top and a bottom, a semiconductor channel located adjacent to the first side, the second side and the bottom of the select gate electrode, and a gate insulating layer located between the channel and the first side, the second side and the bottom of the select gate electrode.