Three-Stage Memory Arrangement for Conflict-Free Data Access
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Solution Overview
Problem
Existing memory arrangements in motor vehicles face challenges in ensuring consistent and conflict-free data packet writing or reading across multiple memory areas accessed by different units, such as sensors and control systems, leading to potential data errors and inefficiencies.
Innovation Solution
A memory arrangement with three interconnected memory areas, a memory control unit, and multiplexer units, which alternates data packet writing between memory areas and ensures read access is prioritized, includes a check-reading unit for error detection and a selective-reading mode to prevent write access during data retrieval, maintaining data integrity and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple memory areas are accessed simultaneously by different memory-accessing units, then data storage capacity and access parallelism are improved, but data consistency and conflict-free access cannot be guaranteed
Solution Approach 1:
The memory system is segmented into three distinct memory areas (first, second, and third memory areas) that can be independently accessed. This segmentation allows different memory-accessing units to write to different memory areas simultaneously without interfering with each other, thus maintaining data consistency while improving parallelism.
Solution Approach 2:
A memory control unit is introduced as an intermediary between memory-accessing units and the memory areas. This mediator manages write access requests, determines which memory area receives data packets, and ensures that read and write operations do not conflict, thereby guaranteeing data consistency across multiple simultaneous accesses.
2Reliability
If read access is prioritized during data retrieval, then data integrity is improved, but write access efficiency may be reduced
Solution Approach 1:
The memory control unit dynamically adjusts access priorities based on the current state of memory areas. When a memory area contains valid data that needs to be read, the control unit prioritizes read access to ensure data integrity. When memory areas are available and no read operations are pending, write access efficiency is maintained by allowing writes to proceed without unnecessary delays.
Solution Approach 2:
The system implements periodic validation of data in memory areas through check-reading units that periodically read and verify data integrity. This periodic action ensures data integrity without continuously blocking write operations, as write access is only restricted when actual read operations are in progress or when validation is currently being performed.
3Reliability
If check-reading units are added for error detection, then data reliability is improved, but device complexity increases
Solution Approach 1:
The check-reading units are merged with the existing memory control unit and multiplexer structure. The same control logic and data pathways are utilized for both regular read operations and check-reading operations, eliminating the need for completely separate verification hardware and reducing overall device complexity while maintaining data reliability.
Solution Approach 2:
The memory control unit is designed with multi-functionality, serving both as the primary controller for read/write operations and as the coordinator for check-reading operations. The multiplexer units also serve dual purposes by routing both regular data access and verification data access through the same physical pathways, reducing hardware complexity while ensuring data reliability through periodic checking.
Data Source
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AI summary
Electronic memory arrangement comprising at least three memory areas (A, B, C), a memory control unit (3) and at least two units (5, 6) which access the memory, wherein at least one unit (6) which accesses the memory can carry out write access operations and at least the other unit (5) which accesses the memory can carry out read access operations, and wherein the memory control unit (3) determines the accesses to the at least three memory areas (A, B, C), wherein the memory control unit (3) is designed in such a manner that, after a data packet has been written to one of the three memory areas (A, B, C), the following data packet to be written is written to a memory area for which no read access operation is simultaneously taking place during this subsequent write access operation.