Three-State Buffer Circuit for Linear ADC Track-and-Hold
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Solution Overview
Problem
Conventional track-and-hold circuits in ADCs face challenges in achieving high linearity and efficiency due to the use of bootstrap switches, which require significant area and power consumption, while also introducing parasitic capacitance and memory effects.
Innovation Solution
A three-state buffer circuit with a voltage follower and switched capacitor circuit that operates in tracking, hold, and reset states, utilizing complementary source followers and simplified switch arrangements to directly drive a sampling capacitor, reducing parasitic capacitance and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If bootstrap switches are used to increase linearity in ADCs, then linearity is improved, but area and power consumption increase significantly
Solution Approach 1:
The patent extracts and eliminates the bootstrap switch component from the traditional T/H circuit architecture. By removing this component, the patent achieves significant reduction in area and power consumption while maintaining linearity through alternative circuit design using complementary source followers and switched capacitor circuitry.
Solution Approach 2:
The complementary source follower circuit performs multiple functions simultaneously: it provides buffering, maintains linearity, and enables track/hold/reset states without requiring separate bootstrap switches. This multi-functional approach consolidates the circuit architecture and reduces overall component count.
2Measurement precision
If bootstrap switches are used to increase linearity in ADCs, then linearity is improved, but power consumption increases significantly
Solution Approach 1:
The patent removes the power-hungry bootstrap switch component and replaces it with a more power-efficient complementary source follower architecture that maintains linearity through its inherent circuit characteristics rather than through active bootstrap switching.
Solution Approach 2:
The patent changes the operating parameters and circuit topology from bootstrap-based switching to complementary source follower-based voltage buffering. This parameter change fundamentally alters how linearity is achieved, shifting from active switching mechanisms to controlled voltage following with lower power dissipation.
3Adaptability or versatility
If conventional T/H circuits are used in ADCs, then basic functionality is achieved, but parasitic capacitance and memory effects are introduced
Solution Approach 1:
The patent converts the potentially harmful parasitic capacitance of switches into a beneficial feature by using switched capacitor circuitry where the parasitic capacitance becomes part of the signal path. The complementary source follower architecture minimizes additional parasitic effects, and the reset functionality actively clears residual charges that could cause memory effects.
Solution Approach 2:
The voltage follower acts as an intermediary buffer between the switched capacitor circuit and the sampling capacitor, isolating parasitic effects and preventing them from degrading signal integrity. This intermediary stage maintains signal fidelity while managing parasitic capacitance effects.
Data Source
AI summary
Presented herein is a three-state buffer circuit having a voltage follower for directly driving a sampling capacitor at an output terminal of the three-state buffer circuit. The three-state buffer circuit further includes a switched capacitor circuit connected at an input of the voltage follower and configured to control the voltage follower to operate in one of a plurality of states. The states are: a tracking state, at which the voltage follower is configured to provide an output voltage at the output terminal at a level corresponding to an input voltage at an input terminal of the three-state buffer circuit; a hold state, at which the voltage follower is configured not to provide any output voltage at the output terminal; and a reset state at which the voltage follower is configured to provide an output voltage at the output terminal at a reset voltage.